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freescale semiconductor, inc. reserves t he right to change the detail specifications, as may be required, to permit improvements in the design of its products. document number: mc13892 rev. 17.0, 05/2012 freescale semiconductor ? freescale semiconductor, inc., 2010 - 2012. all rights reserved. power management integrated circuit (pmic) for i.mx35/51 the mc13892 is a power management integrated circuit (pmic) designed specifically for use with the freescale i.mx35 and i.mx51 families. it is also compatible with the i.mx27, i. mx31, and i.mx37 application processors targeting netbooks, ebooks, smart mobile devices, smart phones, personal media players, and portable navigation devices. features ? battery charger system for wall charging and usb charging ? 10-bit adc for monitoring battery and other inputs, plus a coulomb counter support module ? four adjustable output buck regulators for direct supply of the processor core and memory ? 12 adjustable output ldos with inte rnal and external pass devices ? boost regulator for supplying rgb leds ? serial backlight drivers for displays and keypad, plus rgb led drivers ? power control logic with processor interface and event detection ? real time clock and crystal oscillator circuitry, with coin cell backup and support for external secure real time clock on a companion system processor ic ? touch screen interface ? spi/i 2 c bus interface for control and register access figure 1. mc13892 typical operating circuit power management 13892 vk suffix 98asa10820d 139-pin 7x7mm bga vl suffix 98asa10849d 186-pin 12x12mm bga ordering information see device variation table on page 2. calendar usb li ion battery adapter irda camera ap aud& pwr mgmt tv out camera mc13892 power mgmt & user interface i.mx51 apps processor nvr dram bt (+fm) display backlight spi/i2c ssi ui rtc touch screen mmc ap aud audio ic mic inputs stereo loudspeakers line in/out ui backlight stereo headphones light sensor thermistor power power coin cell battery charger led rgb color indicators calendar calendar usb li ion battery adapter irda camera ap aud& pwr mgmt tv out camera mc13892 power mgmt & user interface i.mx51 apps processor nvr dram bt (+fm) display backlight spi/i2c ssi ui ui rtc touch screen mmc ap aud audio ic mic inputs stereo loudspeakers line in/out ui backlight stereo headphones light sensor thermistor power power coin cell battery charger led rgb color indicators integrated circuit mc13892 power management
analog integrated circuit device data 2 freescale semiconductor mc13892 device variations device variations table 1. mc13892 device variations part number (1) notes package temperature range (t a ) pin map description mc13892cjvk mc13892ajvk (2) 139-pin 7x7 mm bga -40 to +85 c figure 3 global reset function default on (3) mc13892djvk mc13892bjvk (2) (4) global reset function default off (3) mc13892vk mc13892jvk (3) no global reset function (3) mc13892cjvl mc13892ajvl (2) 186-pin 12x12 mm bga figure 4 global reset function default on (3) MC13892DJVL mc13892bjvl (2) (4) global reset function default off (3) mc13892vl mc13892jvl (3) no global reset function (3) notes 1. for tape and reel product, add an ?r2? suffix to the part number. 2. recommended for all new designs 3. not recommended for new designs 4. backward compatible replacement part for mc 13892vk, mc13892jvk, mc13892vl, mc13892jvl, mc13892bjvk, and mc13892bjvl
analog integrated circuit device data freescale semiconductor 3 mc13892 internal block diagram internal block diagram figure 2. mc13892 simplified internal block diagram tsy1 tsy2 bpsns bp resetb resetbmcu wdi standbysec switchers adtrig gndadc adin7 mux 10 bit gp adc int clk32k xtal1 xtal2 gndrtc licell gpo control gpo1 gpo2 rtc + calibration gndsw2 sw2fb sw2out sw1in sw1 1050 ma buck sw2in o/p drive gndsw1 sw1fb sw1out sw3in o/p drive gndsw3 sw3fb sw3out gndswbst swbstfb swbstin swbstout o/p drive pwron1 pums1 monitor timer o/p drive pll 32 khz crystal osc standby gpo3 pwgtdrv1 pwr gate drive & chg pump to interrupt section die temp & thermal warning detection lcell switch enables & control spi result registers interrupt inputs gndctrl core control logic, timers, & interrupts 32 khz internal osc gpo4 chrgctrl1 chrgisns chrgraw chrgled batt battisns battfet bp battery interface & protection licell, uid, die temp, gpo4 adin6 gndchrg clk32kmcu gndreg1 gndreg2 dvs2 dvs1 adin5 a/d result a/d control trigger handling chrgse1b mode dvs control 32 khz buffers chrgctrl2 output pin input pin bi-directional pin package pin legend mc13892 ic charger interface and control : 4 bit dac, clamp, protection, trickle generation pwgtdrv2 spi interface + muxed i2c optional interface cs clk gndspi miso spi registers mosi shift register shift register spivcc to enables & control to trimmed circuits spi control logic trim-in-package startup sequencer decode trim? pums control logic li cell charger sw2 800 ma buck sw3 800 ma buck swbst 300 ma boost voltage / current sensing & translation ledmd ledad ledkp backlight led drive gndbl mc13892 tsx2 tsx1 tsref touch screen interface coulomb counter cfp cfm battisnscc batt ccout to spi sw4in o/p drive gndsw4 sw4fb sw4out sw4 800 ma buck vsrtc vsrtc gndled ledr ledg ledb tri-color led drive vindig vpll viohi pass fet vpll pass fet vdig pass fet vgen1 vdig viniohi viohi vgen1drv vgen1 vcam pass fet vincamdrv vcam vsddrv vsd pass fet vusb2 vvideodrv vvideo vvideo vinusb2 vusb2 spi control vgen2 vgen2drv vgen2 vsd uvbus vinusb vusb uid connector interface best of supply licell bp vgen3 vingen3drv vgen3 reference generation vcoredig gndcore vcore refcore vbus/id detectors vusb regulator otg 5v vbusen vaudio pass fet vaudio gndsub4 gndsub3 gndsub2 gndsub1 gndsub8 gndsub7 gndsub6 gndsub5 gndsub9 gndreg3 vinaudio vinpll pums2 pwron2 pwron3 pass fet
analog integrated circuit device data 4 freescale semiconductor mc13892 pin connections pin connections figure 3. mc13892vk pin connections 12345678910111213 a vusb2 vusb2 vi nusb2 swbsti n gndswbst gndbl nc mode vcore batt chrgraw chrgctrl2 chrgctrl2 b vusb2 gpo1 dvs2 swbstout ledb ledkp ledr gndcore vcoredi g bp chrgctrl1 batti snscc chrgctrl2 c vi npl l vsddrv chrgi sns batti sns d vusb vsd swbstfb ledmd dvs1 refcore chrgse1b li cell battfet bpsns pwron1 e uvbus vpll ledg gndled ui d pums2 gndchrg chrgled pwron2 adtri g i nt gndsw1 f gndsw3 vbusen sw3fb ledad gndsub gndsub gndsub gpo3 gpo2 resetbmcu resetb sw1out g sw3out vi nusb sw4fb gndreg2 gndsub gndsub gndsub pums1 wdi gpo4 sw1i n h sw3i n mi so gndspi gndreg3 gndsub gndsub gndsub gndctrl sw1fb standbysec sw2i n jsw4inmo si clk32kmcu standby gndadc gndreg1 pwron3 tsx1 sw2fb tsx2 sw2out k sw4out spi vcc pwgtdrv1 clk32k vcam cfp cfm adi n5 adi n6 vvi deodrv gndsw2 l gndsw4 cs tsy2 vvideo m vgen3 clk vgen2 vsrtc gndrtc vi ncamdrv pwgtdrv2 vdi g vi ndi g vgen1drv adi n7 tsy1 tsref n vgen3 vgen3 vi ngen3drv vgen2drv xtal2 xtal1 vi naudi o vaudi o vi ohi vi ni ohi vgen1 tsref tsref regulators switchers backlights control logic charger rtc grounds usb adc spi/i2c no connect
analog integrated circuit device data freescale semiconductor 5 mc13892 pin connections figure 4. mc13892vl pin connections 1234567891011121314 a vusb2 vinusb2 swbstout swbstin gndsub nc mode vcore batt chrgraw chrgctrl2 chrgisns regulators b vsddrv gpo1 gndsub gndsub ledr uid dvs1 refcore gndcore chrgse1b bp gndchrg battisnscc battisns switchers c vsd dvs2 swbstfb ledb ledg ledkp ledad pums2 vcoredig licell battfet bpsns gpo3 pums1 backlights d vusb vpll gndsub gndsub gndswbst gndled ledmd gndbl chrgctrl1 chrgled pwron1 pwron3 adtrig gpo4 control logic e uvbus gndreg2 vinpll gndsub gndsub gndsub gndsub gndsub gndsub gndsub pwron2 gpo2 int resetbmcu charger f sw3out vbusen vinusb gndsub gndsub gndsub gndsub gndsub gndsub gndsub gndctrl wdi resetb sw1out rtc g gndsw3 gndsw3 sw3fb gndsub gndsub gndsub gndsub gndsub gndsub gndsub gndsub sw1fb gndsw1 gndsw1 grounds h sw3in sw3in gndsub gndsub gndsub gndsub gndsub gndsub gndsub gndsub sw1in sw1in usb j sw4in sw4in sw4fb gndsub gndsub gndsub gndsub gndsub gndsub sw2fb sw2in sw2in adc k gndsw4 gndsw4 spivcc gndsub gndsub gndsub gndsub gndsub gndsub vvideodrv gndsw2 gndsw2 spi/i2c l sw4out cs gndspi gndsub gndsub gndsub vcam vinaudio vdig gndsub tsy2 standbysec vvideo sw2out no connect m clk vingen3drv clk32kmcu clk32k vsrtc standby vincamdrv cfp cfm vgen1drv vgen1 tsx1 tsx2 tsy1 n vgen3 mosi vgen2 gndreg3 xtal2 xtal1 vaudio pwgtdrv2 viohi viniohi gndadc adin5 adin7 tsref p miso pwgtdrv1 vgen2drv gndsub gndrtc gndsub gndsub gndsub gndsub vindig gndreg1 adin6
analog integrated circuit device data 6 freescale semiconductor mc13892 pin connections table 2. mc13892 pin definitions a functional description of each pin can be found in the functional description . pin number on the 13982vk 7x7 mm pin number on the 13982vl 12x12 mm pin name rating (v) pin function formal name definition a1, a2, b1 a2 vusb2 3.6 output usb 2 supply output regulator for usb phy a3 a3 vinusb2 5.5 power usb 2 supply input input regulator vusb2 a4 a5 swbstin 5.5 power switcher boost power input switcher bst input a5 d5 gndswbst ? ground switcher boost ground ground for switcher bst a6 d8 gndbl ? ground backlight led ground ground for serial led drive a7 a7 nc ? ? no connect do not connect a8 a8 mode 9.0 input mode configuration usb lbp mode, normal mode, test mode selection,& anti-fuse bias a9 a9 vcore 3.6 output core supply regulated supply output for the ic analog core circuitry a10 a10 batt 5.5 input battery connection 1. battery positive pin 2. battery current sensing point 2 3. battery supply voltage sense a11 a11 chrgraw 20 i/o charger input 1. charger input 2. output to battery supplied accesories a12, a13, b13 a12 chrgctrl2 5.5 output charger control 2 driver output for charger path fets m2 b2 b2 gpo1 3.6 output general purpose output 1 general purpose output 1 b3 c2 dvs2 3.6 input dynamic voltage scaling control 2 switcher 2 dvs input pin b4 a4 swbstout 7.5 power switcher boost output switcher bst bp supply b5 c4 ledb 7.5 input led driver general purpose led current sink driver blue b6 c6 ledkp 28 input led driver keypad lighting led current sink driver b7 b5 ledr 7.5 input led driver general purpose led curr ent sink driver red b8 b9 gndcore ? ground core ground ground for the ic core circuitry b9 c9 vcoredig 1.5 output digital core supply regulated supply output for the ic digital core circuitry b10 b11 bp 5.5 power battery plus 1. application supply point 2. input supply to the ic core circuitry 3. application supply voltage sense b11 d9 chrgctrl1 20 output charger control 1 driver output for charger path fets m1 b12 b13 battisnscc 4.8 input battery current sense accumulated current counter current sensing point c1 e3 vinpll 5.5 power pll supply input input regulator processor pll c2 b1 vsddrv 5.5 output vsd driver drive output regulated sd card c12 a13 chrgisns 4.8 input charger current sense charge current sensing point 1 c13 b14 battisns 4.8 input battery current sense battery current sensing point 1
analog integrated circuit device data freescale semiconductor 7 mc13892 pin connections d1 d1 vusb 3.6 output usb supply usb transceiver regulator output d2 c1 vsd 3.6 output sd card supply output regulator sd card d4 c3 swbstfb 3.6 input switcher boost feedback switcher bst feedback d5 d7 ledmd 28 input led driver main display backlight led current sink driver d6 b7 dvs1 3.6 input dynamic voltage scaling control 1 switcher 1dvs input pin d7 b8 refcore 3.6 output core reference main bandgap reference d8 b10 chrgse1b 3.6 input charger select charger forced se1 detection input d9 c10 licell 3.6 i/o coin cell connection 1. coin cell supply input 2. coin cell charger output d10 c11 battfet 4.8 output battery fet connection driver output for battery path fet m3 d12 c12 bpsns 4.8 input battery plus sense 1. bp sense point 2. charge current sensing point 2 d13 d11 pwron1 3.6 input power on 1 power on/off button connection 1 e1 e1 uvbus 20 i/o usb bus 1. usb transceiver cable interface 2. vbus & otg supply output e2 d2 vpll 3.6 output voltage supply for pll output regulator processor pll e4 c5 ledg 7.5 input pwm driver for green led general purpose led current sink driver green e5 d6 gndled ? ground led ground ground for led drivers e6 b6 uid 5.5 input usb id usb otg transceiver cable id e7 c8 pums2 3.6 input power up mode select 2 power up mode supply setting 2 e8 b12 gndchrg ? ground charger ground ground for charger interface e9 d10 chrgled 20 output charger led trickle led driver output 1 e10 e11 pwron2 3.6 input power on 2 power on/off button connection 2 e11 d13 adtrig 3.6 input adc trigger adc trigger input e12 e13 int 3.6 output interrupt signal interrupt to processor e13 g13, g14 gndsw1 ? ground switcher 1 ground ground for switcher 1 f1 g1, g2 gndsw3 ? ground switcher 3 ground ground for switcher 3 f2 f2 vbusen 3.6 input vbus enable external vbus enable pin for otg supply f4 g3 sw3fb 3.6 input switcher 3 feedback switcher 3 feedback f5 c7 ledad 28 input auxiliary display led auxiliary display ba cklight led sinking current driver f6 a6, b3, b4, d3, d4, e4, e5, e6 gndsub1 ? ground ground 1 non critical signal ground and thermal heat sink table 2. mc13892 pin definitions (continued) a functional description of each pin can be found in the functional description . pin number on the 13982vk 7x7 mm pin number on the 13982vl 12x12 mm pin name rating (v) pin function formal name definition
analog integrated circuit device data 8 freescale semiconductor mc13892 pin connections f7 e7, e8, e9, e10, f4, f5, f6 gndsub2 ? ground ground 2 non critical signal ground and thermal heat sink f8 f7, f8, f9, f10, g4, g5, g6, g7, g8 gndsub3 ? ground ground 3 non critical signal ground and thermal heat sink f9 c13 gpo3 ? output general purpose output 3 general purpose output 3 f10 e12 gpo2 3.6 output general purpose output 2 general purpose output 2 f11 e14 resetbmcu 3.6 output mcu reset reset output for processor f12 f13 resetb 3.6 output peripheral reset reset output for peripherals f13 f14 sw1out 5.5 output switcher 1 output switcher 1 output g1 f1 sw3out 5.5 output switcher 3 output switcher 3 output g2 f3 vinusb 7.5 input vusb supply input input option for uvusb; tie to swbst at top level g4 j3 sw4fb 3.6 input switcher 4 feedback switcher 4 feedback g5 e2 gndreg2 ? ground regulator 2 ground ground for regulators 2 g6 g9, g10, g11, h3, h5, h6, h7, h8 gndsub4 ? ground ground 4 non critical signal ground and thermal heat sink g7 h9, h10, h12, j5, j6, j7 gndsub5 ? ground ground 5 non critical signal ground and thermal heat sink g8 j8, j9, j10, k4, k5, k6, k7 gndsub6 ? ground ground 6 non critical signal ground and thermal heat sink g9 c14 pums1 3.6 input power up mode select 1 power up mode supply setting 1 g10 f12 wdi 3.6 input watchdog input watchdog input g12 d14 gpo4 3.6 output general purpose output 4 general purpose output 4 g13 h13, h14 sw1in 5.5 input switcher 1 input input voltage for switcher 1 h1 h1, h2 sw3in 5.5 power switcher 3 input switcher 3 input h2 p2 miso 3.6 i/o master in slave out primary spi read output h4 l3 gndspi ? ground spi ground ground for spi interface h5 n4 gndreg3 ? ground regulator 3 ground ground for regulators 3 h6 k8, k10, l4, l5, l6, l10 gndsub7 ? ground ground 7 non critical signal ground and thermal heat sink h7 p5, p7, p8, p9, p10 gndsub8 ? ground ground 8 non critical signal ground and thermal heat sink h8 ? gndsub9 ? ground ground 9 non critical signal ground and thermal heat sink h9 f11 gndctrl ? ground logic control ground ground for control logic table 2. mc13892 pin definitions (continued) a functional description of each pin can be found in the functional description . pin number on the 13982vk 7x7 mm pin number on the 13982vl 12x12 mm pin name rating (v) pin function formal name definition
analog integrated circuit device data freescale semiconductor 9 mc13892 pin connections h10 g12 sw1fb 3.6 input switcher 1 feedback switcher 1 feedback h12 l12 standbysec 3.6 input secondary standby signal standby input signal from peripherals h13 j13, j14 sw2in 5.5 input switcher 2 input input voltage for switcher 2 j1 j1, j2 sw4in 5.5 power switcher 4 input switcher 4 input j2 n2 mosi 3.6 input master out slave in primary spi write input j4 m3 clk32kmcu 3.6 output 32 khz clock for mcu 32 khz clock output for processor j5 m6 standby 3.6 input standby signal standby input signal from processor j6 n11 gndadc ? ground adc ground ground for a to d circuitry j7 p12 gndreg1 ? ground regulator 1 ground ground for regulators 1 j8 d12 pwron3 3.6 input power on 3 power on/off button connection 3 j9 m12 tsx1 3.6 input touch screen interface x1 touch screen interface x1 j10 j12 sw2fb 3.6 input switcher 2 feedback switcher 2 feedback j12 m13 tsx2 3.6 input touch screen interface x2 touch screen interface x2 j13 l14 sw2out 5.5 output switcher 2 output switcher 2 output k1 l1 sw4out 5.5 output switcher 4 output switcher 4 output k2 k3 spivcc 3.6 input supply voltage for spi supply for spi bus and audio bus k4 p3 pwgtdrv1 4.8 output power gate driver 1 power gate driver 1 k5 m4 clk32k 3.6 output 32 khz clock 32 khz clock output for peripherals k6 l7 vcam 3.6 output camera supply output regulator camera k7 m8 cfp 4.8 passive current filter positive accumulated current filter cap plus pin k8 m9 cfm 4.8 passive current filter negative accumulated current filter cap minus pin k9 n12 adin5 4.8 input adc channel 5 input adc generic input channel 5 k10 p13 adin6 4.8 input adc channel 6 input adc generic input channel 6 k12 k12 vvideodrv 5.5 output vvideo driver drive output regulator vvideo k13 k13, k14 gndsw2 ? ground switcher 2 ground ground for switcher 2 l1 k1, k2 gndsw4 ? ground switcher 4 ground ground for switcher 4 l2 l2 cs 3.6 input chip select primary spi select input l12 l11 tsy2 3.6 input touch screen interface y2 touch screen interface y2 l13 l13 vvideo 3.6 output video supply output regulator tv dac m1, n1, n2 n1 vgen3 3.6 output general purpose regulator 3 output gen3 regulator m2 m1 clk 3.6 input clock primary spi clock input m3 n3 vgen2 3.6 output general purpose regulator 2 output gen2 regulator table 2. mc13892 pin definitions (continued) a functional description of each pin can be found in the functional description . pin number on the 13982vk 7x7 mm pin number on the 13982vl 12x12 mm pin name rating (v) pin function formal name definition
analog integrated circuit device data 10 freescale semiconductor mc13892 pin connections m4 m5 vsrtc 3.6 output srtc supply output regulator for srtc module on processor m5 p6 gndrtc ? ground real time clock ground ground for the rtc block m6 m7 vincamdrv 5.5 i/o camera regulator supply input and driver output 1. input regulator camera using internal pmos fet. 2. drive output regulator for camera voltage using external pnp device. m7 n8 pwgtdrv2 4.8 output power gate driver 2 power gate driver 2 m8 l9 vdig 3.6 output digital supply output regulator digital m9 p11 vindig 5.5 input vdig supply input input regulator digital m10 m10 vgen1drv 5.5 output vgen1 driver drive output gen1 regulator m11 n13 adin7 4.8 input adc channel 7 input adc generic input channel 7, group 1 m12 m14 tsy1 3.6 input touch screen interface y1 touch screen interface y1 m13, n12, n13 n14 tsref 3.6 output touch screen reference touch screen reference n3 m2 vingen3drv 5.5 power/output vgen3 supply input and driver output 1. input vgen3 regulator 2. drive vgen3 output regulator n4 p4 vgen2drv 5.5 output vgen2 driver drive output gen2 regulator n5 n5 xtal2 2.5 input crystal connection 2 32.768 khz oscillator cr ystal connection 2 n6 n6 xtal1 2.5 input crystal connection 1 32.768 khz oscillator cr ystal connection 1 n7 l8 vinaudio 5.5 power audio supply input input regulator vaudio n8 n7 vaudio 3.6 output audio supply output regulator for audio n9 n9 viohi 3.6 output high voltage io supply output regulator high voltage io, efuse n10 n10 viniohi 5.5 input high voltage io supply input input regulator high voltage io n11 m11 vgen1 3.6 output general purpose regulator 1 input gen1 regulator table 2. mc13892 pin definitions (continued) a functional description of each pin can be found in the functional description . pin number on the 13982vk 7x7 mm pin number on the 13982vl 12x12 mm pin name rating (v) pin function formal name definition
analog integrated circuit device data freescale semiconductor 11 mc13892 electrical ch aracteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings charger and usb input voltage (5) v chrgr -0.3 to 20 v mode pin voltage v mode -0.3 to 9.0 v main/aux/keypad current sink voltage v ledmd, v ledad, v ledkp -0.3 to 28 v battery voltage v batt -0.3 to 4.8 v coin cell voltage v licell -0.3 to 3.6 v esd voltage (6) human body model - hbm with mode pin excluded (9) charge device model - cdm v esd 1500 250 v thermal ratings ambient operating temperature range t a -40 to +85 c operating junction temperature range t j -40 to +125 c storage temperature range t stg -65 to +150 c thermal resistance peak package reflow temperature during reflow (7) , (8) t pprt note 8 c notes 5. usb input voltage applies to uvbus pin only 6. esd testing is performed in accordance with the human body model (hbm) (czap = 100 pf, rzap = 1500 ) and the charge device model (cdm), robotic (czap = 4.0 pf). 7. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 8. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. 9. mode pin is not esd protected. table 4. dissipation ratings rating parameter condition symbol vk package vl package unit junction to ambient natural convection single layer board (1s) r ja 104 65 c/w junction to ambient natural convection four layer board (2s2p) r jma 54 42 c/w junction to ambient (@200 ft/min) single layer board (1s) r jma 88 55 c/w junction to ambient (@200 ft/min) four layer board (2s2p) r jma 49 38 c/w junction to board r jb 32 28 c/w junction to case r jc 29 22 c/w junction to package top natural convection jt 7.0 5.0 c/w
analog integrated circuit device data 12 freescale semiconductor mc13892 electrical characteristics static electrical characteristics static electrical characteristics table 5. static electric al characteristics characteristics noted under conditions - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit current consumption rtc mode all blocks disabled, no main battery attached, coin cell is attached to licell (10) rtc i rtc ? 3.00 6.00 a off mode (all blocks disabl ed, main battery attached) (10) mc13892 core and rtc module i off ? 10 30 a power cut mode (all blocks disabled, no main battery attached, coin cell is attached and valid) (10) mc13892 core and rtc module i pcut ? 3.0 6.0 a on standby mode - low-power mode 4 buck regulators in low-power mode, 3 regulators (11) i stby ? 230 295 a on mode - typical use case 4 buck regulators in pwmps mode, 5 regulators (12) i on ? 459 1500 a i/o characteristics (13) pwron1, pwron2, pwron3, pull-up (14) input low, 47 kohm input high, 1.0 mohm 0.0 1.0 ? ? 0.3 vcoredig v chrgse1b, pull-up (15) input low input high 0.0 1.0 ? ? 0.3 vcore v standby, standbysec, wdi, adtrig, weak pull-down (16) , (17) input low input high 0.0 1.0 ? ? 0.3 3.6 v clk32k, cmos output low, -100 a output high, 100 a 0.0 spivcc -0.2 ? ? 0.2 spivcc v clk32kmcu, cmos output low, -100 a output high, 100 a 0.0 vsrtc- 0.2 ? ? 0.2 vsrtc v resetb, resetbmcu, open drain (18) output low, -2.0 ma output high, open drain 0.0 0.0 ? ? 0.4 3.6 v notes 10. valid at 25 c only. 11. vpll, viohi, vgen2 12. vpll, viohi, vgen2, vaudio, vvideo 13. spivcc is typically connected to the output of buck regulator: sw4 and set to 1.800 v 14. input has internal pull-up to vcoredig equivalent to 200 kohm 15. input has internal pull-up to vcore equivalent to 100 kohm 16. spivcc needs to remain enabled for proper detecti on of wdi high to avoid involuntary shutdown 17. a weak pull-down represents a nominal internal pull down of 100 na, unless otherwise noted 18. resetb & resetbmcu have open drain outputs, external pull-ups are required
analog integrated circuit device data freescale semiconductor 13 mc13892 electrical ch aracteristics static electrical characteristics i/o characteristics (continued) (19) vsrtc, voltage output 1.1 ? 1.3 v dvs1, dvs2, weak pull-down (20) input low input high 0.0 0.7* spivcc ? ? 0.3* spivcc 3.1 v gpo1, cmos output low, -400 a output high, 400 a to vcore 0.0 vcore- 0.2 200 ? ? ? 0.2 vcore 500 v ohm gpo2, gpo3, gpo4, cmos output low, -100 a output high, 100 a 0.0 viohi - 0.2 ? ? 0.2 viohi v gpo4, analog input 0.0 ? vcore+0.3 v cs, clk, mosi, vbusen, weak pull-down on cs and vbusen (20) input low input high 0.0 0.7* spivcc ? ? 0.3* spivcc spivcc+0.3 v cs, mosi (at booting for spi / i 2 c decoding), weak pull-down on cs (21) input low input high 0.0 0.7 * vcore ? ? 0.3 * vcore vcore v miso, int, cmos (22) output low, -100 a output high, 100 a 0.0 spivcc -0.2 ? ? 0.2 spivcc v pums1, pums2 (22) pumsxs = 00 pumsxs = 01, load < 10 pf pumsxs = 10 pumsxs = 11 0.0 open 1.3 2.5 ? ? ? ? 0.3 open 2.0 3.1 v mode (23) input low input med input high 0.0 1.1 vcore ? ? ? 0.4 1.7 9.0 v notes 19. spivcc is typically connected to the output of buck regulator: sw4 and set to 1.800 v 20. a weak pull-down represents a nominal internal pull down of 100 na unless otherwise noted 21. the weak pull-down on cs is disabled if a vih is detected at startup to avoid extra consumption in i 2 c mode 22. the output drive strength is programmable 23. input state is latched in first phase of cold start, refer to power control system for description of pums configuration 24. input state is not latched table 5. static elec trical characteristics (continued) characteristics noted under conditions - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 14 freescale semiconductor mc13892 electrical characteristics static electrical characteristics 32 khz crystal oscillator operating voltage oscillator and rtc block from bp v xtal 1.2 ? 4.65 v coincell disconnect threshold at licell v lcd 1.8 ? 2.0 v output low clk32k, clk32kmcu output sink 100 a v clklo 0.0 ? 0.2 v output high clk32k output source 100 a clk32kmcu output source 100 a v clkhi v clkmcuhi spiv cc -0.2 v srtc -0.2 ? ? spiv cc v srtc v vsrtc general operating input voltage range v inmin to v inmax valid coin cell range or valid bp v licell bp 1.8 uvdet ? ? 3.6 4.65 v operating current load range il min to il max i srtc 0.0 ? 50 a bypass capacitor value c srtc ? 1.0 ? f vsrtc active mode ? dc output voltage v out v inmin < v in < v inmax , il min < il < il max v srtc 1.15 1.20 1.25 v clk and miso input low cs, mosi, clk v incslo v inmosilo v inclklo 0.0 ? 0.3*spiv cc v input high cs, mosi, clk v incshi v inmosihi v inclkhi 0.7*spiv cc ? spiv cc +0.3 v output low miso, int output sink 100 a v omisolo v ointlo 0.0 ? 0.2 v output high miso, int output source 100 a v omisohi v ointhi spiv cc -0.2 ? spiv cc v spivcc operating range spiv cc 1.75 ? 3.1 v table 5. static elec trical characteristics (continued) characteristics noted under conditions - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 mc13892 electrical ch aracteristics static electrical characteristics buck regulators operating input voltage pwm operation, 0 < il < i max pfm operation, 0 < il < i max extended pwm or pfm operation (25) v swin 3.0 2.8 uvdet ? ? ? 4.65 4.65 4.65 v output voltage range switcher 1 switchers 2, 3, and 4 v sw1 0.6 0.6 ? ? 1.375 1.850 v output accuracy pwm mode including ripple, load regulation, and transients (26) pfm mode, including ripple, lo ad regulation, and transients v swlopp v swlippi nom-50 nom-50 nom nom nom+50 nom+50 mv maximum continuous load current, i max , v inmin analog integrated circuit device data 16 freescale semiconductor mc13892 electrical characteristics static electrical characteristics buck regulators (continued) automatic mode change threshold, switchover between pfm and pwm modes amc th ? 50 ? ma efficiency pfm, 0.9 v, 1.0 ma pfm, 01.8 v, 1.0 ma pwm pulse skipping, 1.25 v, 50 ma pwm pulse skipping, 1.8 v, 50 ma pwm, 1.25 v, 500 ma pwm, 1.8 v, 500 ma ? ? ? ? ? ? 75 85 78 82 78 82 ? ? ? ? ? ? external components, used as a condition for all other parameters inductor for sw2, sw3, sw4 (28) inductor for sw1 (28) inductor resistance bypass capacitor for sw2, sw3, sw4 (29) bypass capacitor for sw1 (30) bypass capacitor esr input capacitor (31) l sw234 l sw1 r wsw c osw234 c osw1 esr sw -20% -30% ? -35% -35% 5.0 1.0 2.2 1.5 ? 10 2x22 ? 4.7 +20% +30% 0.16 +35% +35% 50 ? h h f f m f swbst average output voltage (32) 3.0 v < v in < 4.65 (1), 0 < il < il max (33) v bst nom-5% 5.0 nom+5% v output ripple 3.0 v < v in < 4.65, 0 < il < il max , excluding reverse recovery of schottky diode v bstpp ? ? 120 mvpp average load regulation v in = 3.6 v, 0 < il < il max v bstlor ? ? 0.5 mv/ma average line regulation 3.0 v < v in < 4.65 v, il = il max v bstlir ? ? 50 mv notes 28. preferred device tdk vls252012 series at 2.5x2.0 mm footprint and 1.2 mm max height 29. preferably 0603 style 6.3 v rated x5r/x7r type at 35% total make tolerance, temperature spread and dc bias derating such as tdk c1608x5r0j106m 30. preferably 0805 style 6.3 v rated x5r/x7r type at 35% total make tolerance, temperature spread and dc bias derating such as tdk c2012x5r0j226m 31. preferably 0603 style 6.3 v rated x5r/x7r type at 35% total make tolerance, temperature spread and dc bias derating such as tdk c1608x5r0j475 32. output voltage when configured to supply vbus in otg mode can be as high as 5.75 v 33. vin is the low side of the inductor that is connected to bp. table 5. static elec trical characteristics (continued) characteristics noted under conditions - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 17 mc13892 electrical ch aracteristics static electrical characteristics swbst (continued) maximum continuous load current il max 3.0 v < v in < 4.65, v out = 5.0 v i bst 300 ? ? ma start-up overshoot il = 0 ma v bstos ? ? 500 mv efficiency, il = il max swbst eff ? 80 ? % external components - used as a condition for all other parameters inductor (34) inductor resistance inductor saturation current at 30% loss in inductance value bypass capacitor (35) bypass capacitor esr at resonance input capacitor diode current capability diode current capability l bst r_w bst il sat co bst esr bst c bstd i bstdpk i bstdpk -20% ? 1.0 -60% 1.0 1.0 850 1500 2.2 ? ? 10 ? 4.7 ? ? +20% 0.2 ? +35% 10 ? ? ? h a f m f madc mapk nmos off leakage, swbstin = 4.5 v, swbsten = 0 i bstik ? 1.0 5.0 a vvideo operating input voltage range v inmin to v inmax v invideo v nom +0.25 ? 4.65 v operating current load range il min to il max (not exceeding pnp max power) i video 0.0 ? 350 ma minimum bypass capacitor value used as a condition for all other parameters co video 1.1 2.2 ? f bypass capacitor esr 10 khz -1.0 mhz esr video 20 ? 100 m vvideo active mode dc output voltage v out v inmin < v in < v inmax , il min < il < il max v video v nom - 3% v nom v nom + 3% v load regulation 1.0 ma < il < il max , for any v inmin < v in < v inmax v videolopp ? ? 0.20 mv/ma line regulation v inmin < v in < v inmax , for any il min < il < il max v videolipp ? 5.0 8.0 mv short-circuit protection threshold v inmin < v in < v inmax , short-circuit v out to gnd i videosht il max +20% ? ? ma notes 34. preferred device tdk vls252012 series at 2.5x2.0 mm footprint and 1.2 mm max height 35. applications of swbst should take into account impact of tolerance and voltage derating on the bypass capacitor at the outpu t level. table 5. static elec trical characteristics (continued) characteristics noted under conditions - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 18 freescale semiconductor mc13892 electrical characteristics static electrical characteristics vvideo low-power mode dc - vvideomode = 1 output voltage v out v inmin < v in < v inmax , il minlp < il < il maxlp v videolo v nom -3% v nom v nom +3% v current load range ilminlp to il maxlp i videolo 0.0 ? 3.0 ma vaudio operating input voltage range v inmin to v inmax v audio v nom +0.25 ? 4.65 v operating current load range il min to il max i audio 0.0 ? 150 ma minimum bypass capacitor value c oaudio 0.65 2.2 ? f bypass capacitor esr 10 khz -1.0 mhz esr audio 0.0 ? 0.1 vaudio active mode dc output voltage v out (v inmin < v in < v inmax , il min < il < il max ) v audio v nom - 3% v nom v nom + 3% v load regulation (1.0 ma < il < il max , for any v inmin < v in < v inmax ) v audiolor ? ? 0.25 mv/ma line regulation v inmin < v in < v inmax , for any il min < il < il max v audiolir ? 5.0 8.0 mv short-circuit protection threshold v inmin < v in < v inmax , short-circuit v out to gnd i audiosht il max +20% ? ? ma vpll and vdig operating input voltage range v inmin to v inmax vdig, vpll all settings, bp biased vpll, vdig [1:0] = 00,01 vpll, vdig [1:0] = 10, 11, external switcher v inpll, v indig uvdet 1.75 2.15 ? sw4 = 1.8 2.2 4.65 4.65 4.65 v operating current load range il min to il max i pll, i dig 0.0 ? 50 ma minimum bypass capacitor value used as a condition for all other parameters c opll, c odig 0.65 2.2 ? f bypass capacitor esr 10 khz -1.0 mhz esr pll , esr dig 0.0 ? 0.1 vpll and vdig active mode dc output voltage v out v inmin < v in < v inmax , il min < il < il max v pll , v dig v nom - 0.05 v nom v nom + 0.05 v load regulation 1.0 ma < il < il max for any v inmin < v in < v inmax v plllor , v diglor ? ? 0.35 mv/ma line regulation v inmin < v in < v inmax for any il min < il < il max v plllir , v diglir ? 5.0 8.0 mv viohi operating input voltage range v inmin to v inmax v nom = 2.775 v v iniohi v nom +0.25 ? 4.65 v operating current load range il min to il max i iohi 0.0 ? 100 ma minimum bypass capacitor value c oiohi 0.65 2.2 ? f bypass capacitor esr 10 khz -1.0 mhz esr iohi 0.0 ? 100 m table 5. static elec trical characteristics (continued) characteristics noted under conditions - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 19 mc13892 electrical ch aracteristics static electrical characteristics viohi active mode dc output voltage v out - (v nom = 2.775) v inmin < v in < v inmax , il min < il < il max v ioh v nom -3% v nom v nom +3% v load regulation 1.0 ma < il < il max , for any v inmin < v in < v inmax v iohlor ? ? 0.35 mv/ma line regulation v inmin < v in < v inmax , for any il min < il < il max v iohlir ? 5.0 8.0 mv vcam operating input voltage range v inmin to v inmax v incam v nom +0.25 ? 4.65 v operating current load range il min to il max internal pass fet external pnp i cam 0.0 0.0 ? ? 65 250 ma minimum bypass capacitor value internal pass device external pnp (not exceeding pnp max power) c ocam 0.65 1.1 2.2 2.2 ? ? f bypass capacitor esr 10 khz -1.0 mhz esr cam 20 ? 100 m vcam active mode dc output voltage v out (v nom = 2.775) v inmin < v in < v inmax , il min < il < il max v cam v nom - 3% v nom v nom + 3% v load regulation 1.0 ma < il < il max , for any v inmin < v in < v inmax v camlor ? ? 0.25 mv/ma line regulation v inmin < v in < v inmax , for any il min < il < il max v camlir ? 5.0 8.0 mv short-circuit protection threshold v inmin < v in < v inmax , short-circuit v out to gnd i camsht il max +20% ? ? ma vcam low-power mode dc output voltage v out v inmin < v in < v inmax , il minlp < il < il maxlp v camlo v nom -3% v nom v nom +3% v current load range il minlp to il maxlp i camlo 0.0 ? 3.0 ma vsd operating input voltage range v inmin to v inmax vsd[2:0] = 010 to 111 vsd[2:0] = 010 to 111, extended operation vsd[2:0] = 000, 001 [000] bp supplied vsd[2:0] = 000 external switcher supplied v insd v nom +0.25 uvdet uvdet 2.15 ? ? ? 2.20 4.65 4.65 4.65 4.65 v operating current load range il min to il max not exceeding pnp max power i sd 0.0 ? 250 ma minimum bypass capacitor value c osd 1.1 2.2 ? f bypass capacitor esr 10 khz -1.0 mhz esr sd 20 ? 100 m table 5. static elec trical characteristics (continued) characteristics noted under conditions - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 20 freescale semiconductor mc13892 electrical characteristics static electrical characteristics vsd active mode dc output voltage v out v inmin < v in < v inmax , il min < il < il max v sd v nom - 3% v nom v nom + 3% v load regulation 1.0 ma < il < il max , for any v inmin < v in < v inmax v sdlor ? ? 0.25 mv/ma line regulation v inmin < v in < v inmax , for any il min < il < il max v sdlir ? 5.0 8.0 mv short-circuit protection threshold v inmin < v in < v inmax , short-circuit v out to gnd i sdsht il max +20% ? ? ma vsd low-power mode dc - vsdmode = 1 output voltage v out v inmin < v in < v inmax , il minlp < il < il maxlp v sdlo v nom -3% v nom v nom +3% v current load range il minlp to il maxlp i sdlo 0.0 ? 3.0 ma vusb general operating input voltage range v inmin to v inmax supplied by vbus supplied by swbst v inusb 4.4 ? 5.0 ? 5.25 5.75 v operating current load range il min to il max i usb 0.0 ? 100 ma bypass capacitor value range c ousb 0.65 2.2 ? f bypass capacitor esr 10 khz -1.0 mhz esr usb 0.0 ? 0.1 vusb active mode dc output voltage v out v inmin < v in < v inmax , il min < il < il max v usb v nom - 4% 3.3 v nom + 4% v load regulation 0 < il < il max from dm/dp for any v inmin < v in < v inmax v usblor ? ? 1.0 mv/ma line regulation v inmin < v in < v inmax , for any il min < il < il max v usblir ? ? 20 mv short-circuit protection threshold v inmin < v in < v inmax , short-circuit v out to gnd v usbsht il max +20% ? ? ma vusb2 operating input voltage range v inmin to v inmax extended operation v inusb2 v nom +0.25 uvdet ? ? 4.65 4.65 v operating current load range il min to il max i usb2 0.0 ? 50 ma minimum bypass capacitor value used as a condition for all other parameters c ousb2 0.65 2.2 ? f bypass capacitor esr 10 khz -1.0 mhz esr usb2 0.0 ? 0.1 table 5. static elec trical characteristics (continued) characteristics noted under conditions - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 21 mc13892 electrical ch aracteristics static electrical characteristics vusb2 active mode dc output voltage v out v inmin < v in < v inmax , il min < il < il max v usb2 v nom -3% v nom v nom + 3% v load regulation 1.0 ma < il < il max , for any v inmin < v in < v inmax v usb2lor ? ? 0.35 mv/ma line regulation v inmin < v in < v inmax , for any il min < il < il max v usb2lir ? 5.0 8.0 mv uvbus operating input voltage range v inmin to v inmax vinusb supplied by swbst v inuvbus 4.75 5.0 5.25 v operating current load range il min to il max i uvbus 0.0 ? 100 ma minimum bypass capacitor value c ouvbus (36) (36) 6.5 (37) f bypass capacitor esr 10 khz -1.0 mhz v inuvbus (36) (36) (37) uvbus active mode dc output voltage vout v inmin < v in < v inmax , il min < il < il max v uvbus 4.4 5.0 5.25 v vgen1 operating input voltage range v inmin to v inmax all settings, bp biased vgen1=00,01, external switcher supplied v ingen1 uvdet < v nom +0.25 2.15 ? 2.2 4.65 4.65 v operating current load range il min to il max (not exceeding pnp max power) i gen1 0.0 ? 200 ma extended input voltage range (bp biased, performance may be out of specification for output levels vgen1[1:0] = 10 to 11) uvdet ? 4.65 v minimum bypass capacitor value c ogen1 1.1 2.2 +35% f bypass capacitor esr 10 khz -1.0 mhz esr gen1 20 ? 100 m vgen1 active mode dc output voltage v out vgen1 = 00, 01, v inmin < v in < v inmax il min < il < il max vgen1 = 10, 11, v inmin < v in < v inmax il min < il < il max v gen1 v nom ? 0.05 v nom ? 3% v nom v nom v nom + 0.05 v nom + 3% v load regulation 1.0 ma < il < il max , for any v inmin < v in < v inmax v gen1lor ? ? 0.25 mv/ma line regulation v inmin < v in < v inmax , for any il min < il < il max v gen1lir ? 5.0 8.0 mv short-circuit protection threshold v inmin < v in < v inmax , short-circuit v out to gnd v gen1sht il max +20% ? ? ma notes 36. filtering is shared with chrgraw (shorted at board level). 2.2 f is typically included at the chrgraw pin. 37. 6.5 f is the maximum allowable capacitance on vbus including all to lerances of filtering capacitan ce on vbus and chrgraw (which are shorted at the board level). table 5. static elec trical characteristics (continued) characteristics noted under conditions - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 22 freescale semiconductor mc13892 electrical characteristics static electrical characteristics vgen1 low-power mode dc - vgen1mode = 1 output voltage v out - v inmin < v in < v inmax , il minlp < il < il maxlp vgen1 = 00, 01 vgen1 = 10, 11 v gen1lo v nom - 0.05 v nom -3% v nom v nom v nom + 0.05 v nom +3% v current load range il minlp to il maxlp i gen1lo 0.0 ? 3.0 ma vgen2 general operating input voltage range v inmin to v inmax all settings, bp biased vgen2=000,001, external switcher supplied v ingen2 uvdet< v nom +0.25 2.15 ? 2.2 4.65 4.65 v operating current load range il min to il max (not exceeding pnp max power) i gen2 0.0 ? 350 ma minimum bypass capacitor value c ogen2 1.1 2.2 +35% f bypass capacitor esr 10 khz -1.0 mhz esr gen2 20 ? 100 m vgen2 active mode dc output voltage v out vgen2 = 000, 001, 010, v inmin < v in < v inmax il min < il < il max vgen2 = 011, 100, 101, 110, 111, v inmin < v in < v inmax il min < il < il max v gen2 v nom -0.05 v nom -3% v nom v nom v nom +0.05 v nom +3% v load regulation 1.0 ma < il < il max , for any v inmin < v in < v inmax v gen2lor ? ? 0.20 mv/ma line regulation v inmin < v in < v inmax , for any il min < il < il max v gen2lir ? 5.0 8.0 mv short-circuit protection threshold v inmin < v in < v inmax , short-circuit v out to gnd v gen2sht il max +20% ? ? ma vgen2 low-power mode dc - vgen2mode=1 output voltage v out - v inmin < v in < v inmax , il minlp < il < il maxlp vgen2 = 000 to 010 vgen2 = 011 to 111 vgen2lo v nom -0.05 v nom -3% v nom v nom v nom +0.05 v nom +3% v current load range il minlp to il maxlp i gen2lo 0.0 ? 3.0 ma vgen3 general operating input voltage range v inmin to v inmax vgen3config, vgen3 = 01, 11 vgen3config, vgen3 = 00, 10 v ingen3 v nom +0.2 uvdet ? ? 4.65 4.65 v operating current load range il min to il max internal pass fet external pnp (not exceeding pnp max power) i gen3 0.0 0.0 ? ? 50 200 ma minimum bypass capacitor value internal pass device external pass device c ogen3 0.65 1.1 2.2 2.2 ? ? f bypass capacitor esr 10 khz -1.0 mhz esr gen3 20 ? 100 m table 5. static elec trical characteristics (continued) characteristics noted under conditions - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 23 mc13892 electrical ch aracteristics static electrical characteristics vgen3 active mode dc output voltage v out vgen2 = 000, 001, 010, v inmin < v in < v inmax il min < il < il max v gen3 v nom -3% v nom v nom + 3% v load regulation 1.0 ma < il < il max , for any v inmin < v in < v inmax v gen3lor ? ? 0.40 mv/ma line regulation v inmin < v in < v inmax , for any il min < il < il max v gen3sht ? 5.0 9.0 mv short-circuit protection threshold v inmin < v in < v inmax , short circuit v out to gnd v gen3sht il max +20% ? ? ma vgen3 low-power mode dc output voltage v out - (accuracy) v inmin < v in < v inmax , il minlp < il < il maxlp v gen3lo v nom -3% v nom v nom +3% v current load range il minlp to il maxlp i gen3lo 0.0 1.0 3.0 ma charge path regulator input operating voltage - chrgraw v inchrg batt min ? 5.6 v output voltage spread - vchrg[2:0]=011, 1xx charge current 1.0 ma to 100 ma charge current 100 ma and above bp sp -1.5 -3.0 ? ? 1.5 1.5 % current limit tolerance (38) ichrg[3:0] = 0001 ichrg[3:0] = 0100 ichrg[3:0] = 0110 all other settings i lim 68 360 500 ? 80 400 560 ? 92 440 620 15 ma ma ma % start-up overshoot - unloaded bp os-start v ? 2.0 % configuration input capacitance - chrgraw (39) load capacitor - bpsns (39) cable length c inchrg c bp l c ? 10 ? 2.2 ? ? ? 47 3.0 f f m thermal thermal warning lower threshold t wl ? 100 ? c thermal warning higher threshold t wh ? 120 ? c thermal warning hysteresis t whys ? 3.0 ? c thermal protection threshold t pt ? 140 ? c backlight led drivers absolute accuracy - all current settings ? ? 15 % matching - at 400 mv, 21 ma ? ? 3.0 % leakage - ledxdc[5:0] = 000000 ? ? 1.0 a signaling led drivers absolute accuracy - all current settings ? ? 15 % matching - at 400 mv, 21 ma ? ? 10 % leakage - ledxdc[5:0] = 000000 ? ? 1.0 a table 5. static elec trical characteristics (continued) characteristics noted under conditions - 40 c t a 85 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 24 freescale semiconductor mc13892 electrical characteristics static electrical characteristics active mode dc output voltage v out - (v nom = 2.775), v inmin < v in < v inmax , il min < il < il max 4.4 5.0 5.25 v adc converter core input range single ended voltage readings differential readings 0.0 -1.2 ? ? 2.4 1.2 v maximum input voltage (40) channels adin5, adin6 and adin7 ? ? bp v integral nonlinearity ? ? 3 lsb differential nonlinearity ? ? 1 lsb zero scale error (offset) after auto calibration ? ? 1 lsb full scale error (gain) after auto calibration ? ? 5 lsb drift over-temperature - including scaling ? ? 1 lsb source impedance no bypass capacitor at input bypass capacitor at input 10 nf ? ? ? ? 5.0 30 k touch screen plate maximum voltage x, y (41) ? ? vcore v plate resistance x, y 100 ? 1000 resistance between plates settling time - contact position measurement 180 3.0 ? ? 1200 5.5 s touch screen in stand alone mode (42) max load current - active mode ? ? 20 ma output voltage - 0.0 analog integrated circuit device data freescale semiconductor 25 mc13892 electrical ch aracteristics dynamic electrical characteristics dynamic electrical characteristics table 6. dynamic electri cal characteristics characteristics noted under conditions 3.1 v batt 4.65 v, -40 t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit 32 khz crystal oscillator rtc oscillator start-up time upon application of power t rtcst ? ? 1.0 sec clk32k rise and fall time - cl = 50 pf clk32kdrv[1:0] = 00 (default) clk32kdrv[1:0] = 01 clk32kdrv[1:0] = 10 clk32kdrv[1:0] = 11 t clk32ket ? ? ? ? 22 11 high z 44 ? ? ? ? ns clk32kmcu rise and fall time cl = 12 pf t clk32kmcuet ? 22 ? ns clk32k and clk32kmcu output duty cycle crystal on xtal1, xtal2 pins t clk32kdc , t clk32kmcudc 45 ? 55 % clk and miso miso rise and fall time, cl = 50 pf, spivcc = 1.8 v spidrv [1:0] = 00 (default) spidrv [1:0] = 01 spidrv [1:0] = 10 spidrv [1:0] = 11 t misoet ? ? ? ? 11 6.0 high z 22 ? ? ? ? ns buck regulators turn-on time, enable to 90% of end value, il = 0 t onpwm ? ? 500 s swbst turn-on time enable to 90% of v out , il = 0 t onbst ? ? 2.0 ms transient load response, il from 1.0 ma to 100 ma in 1.0 s steps maximum transient amplitude time to settle 80% of transient a tmax ? ? ? ? 300 500 mv s transient load response, il from 100 ma to 1.0 ma maximum transient amplitude time to settle 80% of transient a tmax ? ? ? ? 300 20 mv s vvideo active mode - ac psrr - il = 75% of il max , 20 hz to 20 khz v in = v inmin + 100 mv v in = v nom + 1.0 v v videopssr 35 50 40 60 ? ? db max output noise - v in = v inmin , il = 75% of il max 100 hz ? 1.0 khz >1.0 khz ? 10 khz >10 khz ? 1.0 mhz v videoon ? ? ? -114 -124 -129 ? ? ? dbv/ hz turn-on time enable to 90% of end value, v in = v inmin , v inmax , il = 0 vvideot on ? ? 1.0 ms vvideo active mode - ac (continued) turn-off time disable to 10% of initial value, v in = v inmin , v inmax , il = 0 vvideot off 0.1 ? 10 ms transient load response v in = v inmin , v inmax v videotlor ? 1.0 2.0 %
analog integrated circuit device data 26 freescale semiconductor mc13892 electrical characteristics dynamic electrical characteristics transient line response il = 75% of il max v videotlir ? 5.0 8.0 mv mode transition time from low-power to active, v in = v inmin , v inmax , il = il maxlp vvideot mod ? ? 100 s mode transition response from low-power to active and from active to low-power, v in = v inmin , v inmax , il = il maxlp v videomtr ? 1.0 2.0 % vaudio psrr - il = 75% of il max , 20 hz to 20 khz v in = v inmin + 100 mv, > uvdet v in = v nom + 1.0 v, > uvdet v audiopssr 35 50 40 60 ? ? db max output noise - v in = v inmin , il = 0.75*ilmax 100 hz ? 1.0 khz >1.0 khz ? 10 khz >10 khz ? 1.0 mhz v audioon ? ? ? -114 -124 -129 ? ? ? dbv/ hz turn-on time enable to 90% of end value, v in = v inmin , v inmax , il = 0 vaudiot on ? ? 1.0 ms turn-off time disable to 10% of initial value, v in = v inmin , v inmax , il = 0 vaudiot off 0.1 ? 10 ms transient load response - see transient waveforms on page 84 , v in = v inmin , v inmax v audiotlor ? 1.0 2.0 % transient line response - see transient waveforms on page 84 il = 75% of il max v audiotlir ? 5.0 8.0 mv vpll and vdig active mode - ac psrr - il = 75% of il max , 20 hz to 20 khz v in = uvdet v in = v nom + 1.0 v, > uvdet vpllpssr 35 50 40 60 ? ? db output noise - v in = v inmin , il = 0.75*il max 100 hz ? 1.0 khz >1 khz ? 1.0 mhz vpllon ? ? 20 2.5 ? ? db/dec v/ hz turn-on time enable to 90% of end value, v in = v inmin , v inmax , il = 0 vpllt on ? ? 100 s turn-off time disable to 10% of initial value, v in = v inmin , v inmax , il = 0 vpllt off 0.1 ? 10 ms transient load response - see transient waveforms on page 84 v in = v inmin , v inmax v plltlor , v digtlor ? 50 70 mv transient line response - see transient waveforms on page 84 il = 75% of il max v plltlir , v digtlir ? 5.0 8.0 mv table 6. dynamic elec trical characteristics (continued) characteristics noted under conditions 3.1 v batt 4.65 v, -40 t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 27 mc13892 electrical ch aracteristics dynamic electrical characteristics viohi active mode - ac psrr - il = 75% of il max , 20 hz to 20 khz v in = v inmin + 100 mv, > uvdet v in = v nom + 1.0 v, > uvdet v iohipssr 35 50 40 60 ? ? db output noise - v in = v inmin , il = 0.75*il max 100 hz ? 1.0 khz >1.0 khz ? 1.0 mhz v iohion ? ? 20 1.0 ? ? db/dec v/ hz turn-on time enable to 90% of end value, v in = v inmin , v inmax , il = 0 viohit on ? ? 1.0 ms turn-off time disable to 10% of initial value, v in = v inmin , v inmax , il = 0 viohit off 0.1 ? 10 ms transient load response - see transient waveforms on page 84 v in = v inmin , v inmax v iohitlor ? 1.0 2.0 % transient line response - see transient waveforms on page 84 il = 75% of il max v iohitlir ? 5.0 8.0 mv mode transition time - see transient waveforms on page 84 from low-power to active, v in = v inmin , v inmax , il = il maxlp v iohimtr ? ? 10 s mode transition response from low-power to active and from active to low-power, v in = v inmin , v inmax , il = il maxlp v iohimtr ? 1.0 2.0 % vcam active mode - ac psrr - il = 75% of il max , 20 hz to 20 khz v in = v inmin + 100 mv v in = v nom + 1.0 v v campssr 35 50 40 60 ? ? db output noise - v in = v inmin , il = 0.75*il max 100 hz ? 1.0 khz >1.0 khz ? 1.0 mhz v camon ? ? 20 1.0 ? ? db/dec v/ hz turn-on time (enable to 90% of end value, v in = v inmin , v inmax , il = 0) vcamt on ? ? 1.0 ms turn-off time (disable to 10% of initial value, v in = v inmin , v inmax , il = 0) vcamt off 0.1 ? 10 ms transient load response - see transient waveforms on page 84 v in = v inmin , v inmax vcam = 01, 10, 11 vcam = 00 v camlor ? ? 1.0 50 2.0 70 % mv transient line response - see transient waveforms on page 84 il = 75% of il max v camlir ? 5.0 8.0 mv mode transition time - see transient waveforms on page 84 from low-power to active, v in = v inmin , v inmax , il = il maxlp vcamt mod ? ? 100 s mode transition response from low-power to active and from, active to low-power, v in = v inmin , v inmax , il = il maxlp v cammtr ? 1.0 2.0 % table 6. dynamic elec trical characteristics (continued) characteristics noted under conditions 3.1 v batt 4.65 v, -40 t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 28 freescale semiconductor mc13892 electrical characteristics dynamic electrical characteristics vsd active mode - ac psrr - il = 75% of il max , 20 hz to 20 khz v in = v inmin + 100 mv v in = v nom + 1.0 v v sdpssr 35 50 40 60 ? ? db max output noise - v in = v inmin , il = 75% of il max 100 hz ? 1.0 khz >1.0 khz ? 10 khz >10 khz ? 1.0 mhz v sdon ? ? ? -115 -126 -132 ? ? ? dbv/ hz turn-on time (enable to 90% of end value, v in = v inmin , v inmax , il = 0) vsdt on ? ? 1.0 ms turn-off time (disable to 10% of initial value, v in = v inmin , v inmax , il = 0) vsdt off 0.1 ? 10 ms transient load response - see transient waveforms on page 84 v in = v inmin , v inmax - vsd[2:0] = 010 to 111 - vsd[2:0] = 000 to 001 v sdtlor ? ? 1.0 ? 2.0 70 % mv transient line response - see transient waveforms on page 84 il = 75% of il max v sdtlir ? 5.0 8.0 mv mode transition time - see transient waveforms on page 84 from low-power to active, v in = v inmin , v inmax , il = il maxlp vsdt mod ? ? 100 s mode transition response - see transient waveforms on page 84 from low-power to active and from active to low-power, v in = v inmin , v inmax , il = il maxlp v sdmtr ? 1.0 2.0 % vusb active mode - ac psrr - il = 75% of il max , 20 hz to 20 khz v in = v inmin + 100 mv v usbpssr 35 40 ? db max output noise - v in = v inmin , il = 75% of il max 100 hz ? 50 khz >50 khz ? 1.0 mhz v usbon ? ? 1.0 0.2 ? ? v/ hz vusb2 active mode - ac psrr - il = 75% of il max , 20 hz to 20 khz v in = v inmin + 100 mv v in = v nom + 1.0 v v usb2pssr 35 50 40 60 ? ? db output noise - v in = v inmin , il = 0.75*il max 100 hz ? 1.0 khz >1.0 khz ? 1.0 mhz v usb2on ? ? 20 0.2 ? ? db/dec v/ hz turn-on time enable to 90% of end value, v in = v inmin , v inmax , il = 0 vusb2t on ? ? 100 s turn-off time disable to 10% of initial value, v in = v inmin , v inmax , il = 0 vusbt off 0.1 ? 10 ms start-up overshoot v in = v inmin , v inmax , il = 0 v usb2os ? 1.0 2.0 % transient load response - see transient waveforms on page 84 v in = v inmin , v inmax v usb2tlor ? 1.0 2.0 % transient line response - see transient waveforms on page 84 il = 75% of il max v usb2tlir ? 5.0 8.0 mv table 6. dynamic elec trical characteristics (continued) characteristics noted under conditions 3.1 v batt 4.65 v, -40 t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 29 mc13892 electrical ch aracteristics dynamic electrical characteristics uvbus active mode dc turn-on time vbus rise time per usb otg with max loading of 6.5 f+10 f uvbust on ? ? 100 ms turn-off time disable to 0.8 v, per usb otg specification parameter va_sess_vld, v in = v inmin , v inmax , il = 0 uvbust off ? ? 1.3 sec vgen1 active mode - ac psrr - il = 75% of il max , 20 hz to 20 khz v in = uvdet v in = v nom + 1.0 v, > uvdet v gen1pssr 35 50 40 60 ? ? db max output noise - v in = v inmin , il = 0.75*il max 100 hz ? 1.0 khz >1.0 khz ? 10 khz >10 khz ? 1.0 mhz v gen1on ? ? ? -115 -126 -132 ? ? ? dbv/ hz turn-on time enable to 90% of end value v in = v inmin , v inmax , il = 0 vgen1t on ? ? 1.0 ms turn-off time disable to 10% of initial value v in = v inmin , v inmax , il = 0 vgen1t off 0.1 ? 10 ms transient load response - see transient waveforms on page 84 v in = v inmin , v inmax - vgen1[1:0] = 10 to 11 - vgen[1:0] = 00 to 01 v gen1tlor ? ? 1.0 ? 3.0 70 % mv transient line response - see transient waveforms on page 84 il = 75% of il max v gen1tlir ? 5.0 8.0 mv mode transition time - see transient waveforms on page 84 from low-power to active v in = v inmin , v inmax , il = il maxlp vgen1t mod ? ? 100 s mode transition response - see transient waveforms on page 84 from low-power to active and from active to low-power v in = v inmin , v inmax , il = il maxlp v gen1mtr ? 1.0 2.0 % vgen2 active mode - ac psrr - il = 75% of il max , 20 hz to 20 khz v in = v inmin + 100 mv v in = v nom + 1.0 v v gen2pssr 35 50 40 60 ? ? db max output noise - v in = v inmin , il = il max 100 hz ? 1.0 khz >1.0 khz ? 10 khz >10 khz ? 1.0 mhz v gen2on ? ? ? -115 -126 -132 ? ? ? dbv/ hz turn-on time enable to 90% of end value v in = v inmin , v inmax , il = 0 vgen2t on ? ? 1.0 ms turn-off time (disable to 10% of initial value v in = v inmin , v inmax , il = 0) vgen2t off 0.1 ? 10 ms transient load response - see transient waveforms on page 84 v in = v inmin , v inmax - vgen2[2:0] = 100 to 111 - vgen2[2:0] = 000 to 011 v gen2tlor ? ? 1.0 ? 3.0 70 % mv transient line response - see transient waveforms on page 84 il = 75% of il max v gen2tlir ? 5.0 8.0 mv table 6. dynamic elec trical characteristics (continued) characteristics noted under conditions 3.1 v batt 4.65 v, -40 t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 30 freescale semiconductor mc13892 electrical characteristics dynamic electrical characteristics vgen2 active mode - ac (continued) mode transition time - see transient waveforms on page 84 from low-power to active v in = v inmin , v inmax , il = il maxlp vgen2t mod ? ? 100 s mode transition response - see transient waveforms on page 84 from low-power to active and from active to low-power v in = v inmin , v inmax , il = il maxlp v gen2mtr ? 1.0 2.0 % vgen3 active mode - ac psrr il = 75% of il max , 20 hz to 20 khz, v in = v inmin +100 mv v in = v nom +1.0 v v gen3pssr 35 45 40 50 ? ? db output noise - v in = v inmin , il = 75% of il max 100 hz ? 1.0 khz >1.0 khz ? 1.0 mhz v gen3on ? ? 20 1.0 ? ? db/dec v/ hz turn-on time enable to 90% of end value v in = v inmin , v inmax , il = 0 vgen3t on ? ? 1.0 ms turn-off time disable to 10% of initial value v in = v inmin , v inmax , il = 0 vgen3t off 0.1 ? 5.0 ms transient load response v in = v inmin , v inmax - vgen3 = 1 - vgen3 = 0 v gen3tlor ? ? 1.0 ? 2.0 70 % mv transient line response (il = 75% of il max ) v gen3tlir ? 5.0 8.0 mv mode transition time from low-power to active v in = v inmin , v inmax , il = il maxlp vgen3t mod ? ? 100 s mode transition response from low-power to active and from active to low-power, v in = v inmin , v inmax , il = il maxlp v gen3mtr ? 1.0 2.0 % uvbus - active mode dc turn-on time - vbus rise time por usb otg with max loading of 6.5 f+10 f ? ? 100 ms turn-off time - disable to 0.8 v, per usb otg specification parameter va_sess_vld v in = v inmin , v inmax , il=0 ? ? 1.3 sec adc conversion time per channel - pllx[2:0] = 100 ? ? 10 s turn on delay if switcher pll was active if switcher pll was inactive ? ? 0.0 5.0 ? 10 s touch screen turn-on time - 90% of output ? ? 500 s table 6. dynamic elec trical characteristics (continued) characteristics noted under conditions 3.1 v batt 4.65 v, -40 t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 31 mc13892 functional description functional pin description functional description functional pin description charger chrgraw 1. charger input. the charger voltage is measured through an adc at this pin. the uvbus pin must be shorted to chrgraw in cases where the charger is being supplied from the usb c able. the minimum voltage for this pin depends on battmin threshold value (see battery interface and control ). 2. output to battery supplied accessories. the battery voltag e can be applied to an accessory by enabling the charge path for the accessory via the chrgraw pin. to accomplish this, the charger needs to be configured in reverse supply mode. chrgctrl1 driver output for charger path fet m1. chrgctrl2 driver output for charger path fet m2. chrgisns charge current sensing point 1. the charge current is read by monitoring the voltage drop over the charge current 100 m sense resistor connected between chrgisns and bpsns. bpsns 1. bp sense point. bp voltage is sensed at this pin and compared with the voltage at chrgraw. 2. charge current sensing point 2. the charge current is re ad by monitoring the voltage drop over the charge current 100 m sense resistor. this resistor is connected between chrgisns and bpsns. bp this pin is the application supply point, the input supply to the ic core circuitry. the application supply voltage is sensed through an adc at this pin. battfet driver output for battery path fet m3. if no charging system is required or single pa th is implemented, the pin battfet must be floating. battisns battery current sensing point 1. the current flowing out of a nd into the battery can be read via the adc by monitoring the voltage drop over the sense resi stor between bat t and battisns. batt battery positive terminal. battery current sensing point 2. the supply voltage of the battery is sensed through an adc on this pin. the current flowing out of and into t he battery can be read via the adc by monito ring the voltage drop over the sense resi stor between batt and battisns. battisnscc accumulated current counter current sensi ng point. this is the coulomb counter current sense point. it should be connected directly to the 0.020 sense resistor via a separate route from battisns. the coulomb counter monitors the current flowing in/ out of the battery by integrating the voltage drop ov er the battisncc and the batt pin.
analog integrated circuit device data 32 freescale semiconductor mc13892 functional description functional pin description cfp and cfm accumulated current filter cap plus and minus pins respectively. the coulomb counter will require a 10 f output capacitor connected between these pins to perform a fi rst order filtering of the signal across r1. chrgse1b an unregulated wall charger configuration c an be built in which case this pin must be pulled low. when charging through usb, it can be left open since it is internally pulled up to vcore. the recommendation is to place an external fet that can pull it low or left it open, depending on the charge method. chrgled trickle led driver output 1. since normal led control via the spi bus is not always possible in the standalone operation, a current sink is provided at the chrgled pin. this led is to be connected between this pin and chrgraw. gndchrg ground for charger interface. ledr, ledg and ledb general purpose led driver output red, gr een and blue respectively. each channel provides flexible led intensity control. these pins can also be used as general purpose open drain out puts for logic signaling, or as generic pwm generator outputs. gndled ground for led drivers ic core vcore regulated supply output for the ic analog core circuitry. it is used to define the pums vih level during initialization. the bandgap and the rest of the core circuitr y are supplied from vcore. place a 2.2 f capacitor from this pin to gndcore. vcoredig regulated supply output for the ic digital core circuitry. no external dc loading is allowed on vcoredig. vcoredig is kept powered as long as there is a valid supply and/or coin cell. place a 2.2 f capacitor from this pin to gndcore. refcore main bandgap reference. all regulators use the main bandgap as the reference. the main bandgap is bypassed with a capacitor at refcore. no external dc l oading is allowed on refcore. place a 100 nf capacitor from this pin to gndcore. gndcore ground for the ic core circuitry. power gating pwgtdrv1 and pwgtdrv2 power gate drivers. pwgtdrv1 is provided for power gating peripheral loads shari ng the processor core supply domain(s) sw1, and/or sw2, and/or sw3. in addition, pwgtdrv2 provides support to power gate peripheral loads on the sw4 supply domain. in typical applications, sw1, sw2, and sw3 will both be kept ac tive for the processor modules in state retention, and sw4 retained for the external memory in self refresh mode. sw1, sw2, and sw3 power gating fet drive would typically be connected to pwgtdrv1 (for parallel nmos switches). sw4 power gating fet drive would typically be connected to pwgtdrv2. when low-power off mode is activated, the powe r gate drive circuitry will be disabled, turn ing off the nmos power gate switches to isolate the maintained supply domains from any peripheral loading.
analog integrated circuit device data freescale semiconductor 33 mc13892 functional description functional pin description switchers sw1in, sw2in, sw3in and sw4in switchers 1, 2, 3, and 4 input. connect these pins to bp to supply switchers 1, 2, 3, and 4. sw1fb, sw2fb, sw3fb and sw4fb switchers 1, 2, 3, and 4 feedback. switchers 1, 2, 3, and 4 output voltage sense respecti vely. connect these pins to the farthe r point of each of their respective swxout pin, in order to sense and maintain voltage stability. sw1out switcher 1 output. buck regu lator for processor core(s). gndsw1 ground for switcher 1. sw2out switcher 2 output. buck regulator for processor sog, etc. gndsw2 ground for switcher 2. sw3out switcher 3 output. buck regulator for internal processor memory and peripherals. gndsw3 ground for switcher 3. sw4out switcher 4 output. buck regulator for external memory and peripherals. gndsw4 ground for switcher 4. dvs1 and dvs2 switcher 1 and 2 dvs input pins. provided for pin controlled d vs on the buck regulators targeted for processor core supplies. the dvs pins may be reconfigured for switcher increment / decr ement (sid) mode control. when transitioning from one voltage to another, the output voltage slo pe is controlled in steps of 25 mv per time step. these pins must be set high in order for the dvs feature to be enabled for each of switchers 1 or 2, or low to disable it. swbstin switcher bst input. the 2.2 h switcher bst inductor must be connected here. swbstout power supply for gate driver for the internal power nmos that charges swbst inductor. it must be connected to bp. swbstfb switcher bst feedback. when swbst is configured to supply the uvbus pin in otg mode the feedback will be switched to sense the uvbus pin instead of the swbstfb pin. gndswbst ground for switcher bst.
analog integrated circuit device data 34 freescale semiconductor mc13892 functional description functional pin description regulators viniohi input of viohi regulator. connec t this pin to bp in order to supply viohi regulator. viohi output regulator for high voltage io. fixed 2.775 v output for high-voltage level interface. vinpll and vindig the input of the regulator for processor pll and digital regu lators respectively. vindig and vinpll can be connected to either bp or a 1.8 v switched mode power supply rail, such as from sw4 fo r the two lower set points of each regulator (the 1.2 and 1.25 v output for vpll, and 1.05 and 1.25 v output for vdig). in addition, when the two upper set points are used (1.50 and 1.8 v outputs for vpll, and 1.65 and 1.8 v for vdig), they can be connected to either bp or a 2.2 v nominal external switched mode power supply rail, to improve power dissipation. vpll output of regulator for processor pll. quiet analog supply (pll, gps). vdig output regulator digital. low voltage digital (dpll, gps). vvideodrv drive output for vvideo external pnp transistor. vvideo output regulator tv dac. this pin must be connected to the collector of the external pnp transisto r of the vvideo regulator. vinaudio input regulator vaudio. ty pically connected to bp. vaudio output regulator for audio supply. vinusb2 input regulator vusb2. this pin must always be connected to bp even if the regulators are not used by the application. vusb2 output regulator fo r powering usb phy. vincamdrv 1. input regulator camera using internal pmos fet. typically connected to bp. 2. drive output regulator for camera voltage using external pnp device. in this case, this pin must be connected to the base of the pnp in order to drive it. vcam output regulator for the camera module. when using an external pnp device, this pin must be connected to its collector. vsddrv drive output for the vsd external pnp transistor. vsd output regulator for multi-media cards such as micro sd, rs-mmc.
analog integrated circuit device data freescale semiconductor 35 mc13892 functional description functional pin description vgen1drv drive output for the vgen1 external pnp transistor. vgen1 output of general purpose 1 regulator. vgen2drv drive output for the vgen2 external pnp transistor. vgen2 output of general purpose 2 regulator. vingen3drv 1. input for the vgen3 regulator when no external pnp transistor used. typically connected to bp. 2. drive output for vgen3 in case an external pnp transisto r is used on the application. in this case, this pin must be connected the base of the pnp transistor. vgen3 output of general purpose 3 regulator. vsrtc output regulator for the srtc module on the processor. th e vsrtc regulator provides the clk32kmcu output level (1.2 v). additionally, it is used to bias the low-power srtc domain of the srtc module integrated on certain fsl processors. gndreg1 ground for regulators 1. gndreg2 ground for regulators 2. gndreg3 ground for regulators 3. general outputs gpo1 general purpose output 1. intended to be used for ba ttery thermistor biasing. in this case, connect a 10 k resistor from gpo1 to adin5, and one from adin5 to gnd. gpo2 general purpose output 2. gpo3 general purpose output 3. gpo4 general purpose output 4. it c an be configured for a muxed connection into channel 7 of the gp adc.
analog integrated circuit device data 36 freescale semiconductor mc13892 functional description functional pin description control logic licell coin cell supply input and charger output. the licell pin provides a connection for a coin cell backup battery or supercap. if the main battery is deeply discharged, removed, or contac t-bounced (i.e., during a power cut), the rtc system and coin cell maintained logic will switch over to the licell for backup power. this pin also works as a curr ent-limited voltage source for battery charging. a small capacitor should be placed from licell to ground under all circumstances. xtal1 32.768 khz oscillator crystal connection 1. xtal2 32.768 khz oscillator crystal connection 2. gndrtc ground for the rtc block. clk32k 32 khz clock output for peripherals. at system start-up, the 32 khz clock is driven to clk32k (provided as a peripheral clock reference), which is referenced to spivcc. the clk32k is restricted to state machine activation in normal on mode. clk32kmcu 32 khz clock output for processo r. at system start-up, the 32 khz clock is driven to clk32kmcu (intended as the ckil input to the system processor) referenced to vsrtc. the driver is enabled by the start-up sequencer and the clk32kmcu is programmable for low-power off m ode control by the state machine. resetb and resetbmcu reset output for peripherals and processor respectively . these depend on the power cont rol modes of operation ( see functional device operation on page 40 ). these are meant as reset for the processor, or peripherals in a power up condition, or to keep one in reset while the other is up and running. wdi watchdog input. this pin must be high to stay in the on m ode. the wdi io supply voltage is referenced to spivcc (normally connected to sw4 = 1.8 v). spivcc must therefore remain enabled to allow for proper wdi detection. if wdi goes low, the system will transition to the off state or co ld start (depending on the configuration). standby and standbysec standby input signal from processor and from peripherals respectively. to ensure that shared resources are properly powered when requir ed, the system will only be allowed into standby when both the application processor (which typically controls the stand by pin) and peripherals (which typically control the standbysec pin) allow it. this is referred to as a standby event. the standby pins are programmable for active high or active low polarity, and that decoding of a standby event will take into account the programmed input polarities associated with each pin. since the standby pin activity is driven asynchronously to th e system, a finite time is required for the internal logic to qualify and respond to the pin level changes. the state of the standby pins only have influence in the on mode and are therefore ignored during start up and in the watchdog phase. this allows the system to power up without c oncern of the required standby polarities, since software can make adjustments accordingly, as soon as it is running. int interrupt to processor. unmasked interrupt events are signaled to the processor by driving the int pin high.
analog integrated circuit device data freescale semiconductor 37 mc13892 functional description functional pin description pwron1, 2 and 3 a turn on event can be accomplished by connecting an open drain nmos driver to the pwronx pin of the mc13892, so that it is in effect a parallel path for the power key. in addition to the turn on event, the mc13892a/b/c/d ve rsions include a global reset feature on the pwron3 pin. on the a/b/c/d versions, the glbrstenb defaults to 0. in th e mc13892a/c versions global reset is active low. since glbrstenb defaults to 0, the global reset f eature is enabled by default. in the mc13892b/d versions global reset is active high . since glbrstenb defaults to 0, the global reset feature is di sabled by default. the global reset function can be enabled or disabled by changing the spi bit glbrstenb at any time, as shown in table below: the global reset feature powers down the part, disables the char ger, resets the spi registers to their default value and then powers back on. to generate a global reset, the pwron3 pin needs to be pulled low for greater than 12 seconds and then pulled back high. if the pwron3 pin is held low for less t han 12 seconds, the pin will act as a normal pwron pin. pums1 and pums2 power up mode supply setting. default start-up of the device is selectable by hardwiring the power up mode select pins. the power up mode select pins (pums1 and pums2) are used to conf igure the start-up characterist ics of the regulators. supply enabling and output level options ar e selected by hardworking the pums pins for the desired configuration. mode usb lbp mode, normal mode, test mode selection & anti-fuse bi as. during evaluation and testi ng, the ic can be configured for normal operation or test mode via the mode pin as summarized in the following table. gndctrl ground for control logic. spivcc supply for spi bus and audio bus cs cs held low at cold start configures the interface for spi mode. once activated, cs functions as the spi ch ip select. cs tied to vcore at cold start configures the interface for i 2 c mode; the pin is not used in i 2 c mode other than for configuration. because the spi interface pins can be reconfigured for reuse as an i 2 c interface, a configuration protocol mandates that the cs pin is held low during a turn on event for the ic (a weak pull-down is integrated on the cs pin). device global reset function glbrstenb configuration glbrstenb mc13892 no n/a n/a mc13892a yes active low 0 = enabled (default) 1 = disabled mc13892b yes active hi 0 = disabled (default) 1 = enabled mc13892c yes active low 0 = enabled (default) 1 = disabled mc13892d yes active hi 0 = disabled (default) 1 = enabled mode pin state mode ground normal operation vcoredig usb low-power boot allowed vcore test mode
analog integrated circuit device data 38 freescale semiconductor mc13892 functional description functional pin description clk primary spi clock input. in i 2 c mode, this pin is the scl signal (i 2 c bus clock). mosi primary spi write input. in i 2 c mode, the mosi pin hard wired to ground or vcore is used to select between two possible addresses (a0 address selection). miso primary spi read output. in i 2 c mode, this pin is the sda signal (bi-directional serial data line). gndspi ground for spi interface. usb uid this pin identifies if a mini-a or mini-b style plug has been connected to the applicat ion. the state of th e id detection can b e read via the spi, to poll dedicated sense bits for a float ing, grounded, or factory mode condition on the uid pin. uvbus 1. usb transceiver cable interface. 2. otg supply output. when swbst is configured to supply the uvbus pin in otg mo de, the feedback will switch to sense the uvbus pin instead of the swbstfb pin. vusb this is the regulator used to provide a voltage to an external usb transceiver ic. vinusb input option for vusb; supplied by swbst. this pin is internal ly connected to the uvbus pin for otg mode operation (for more details about otg mode). note: when vusbin = 1, uvbus will be connected via internal switches to vinusb and incur some current drain on that pin, as much as 270 a maximum, so care must be taken to disable this path and set this spi bit (vusbin) to 0 to minimize current drain, even if swbst and/or vusb are disabled. vbusen external vbus enable pin for the otg supply. vbus is defined as the power rail of the usb cable (+5.0 v). a to d converter note: the adin5/6/7 inpu ts must not exceed bp. adin5 adc generic input channel 5. adin5 may be used as a general purpose unscaled input, but in a typical application, adin5 is used to read out the battery pack thermistor. the thermistor mu st be biased with an external pull-up to a voltage rail greater than the adc input range. in order to save curre nt when the thermistor reading is not requ ired, it can be biased from one of the gen eral purpose ios such as gpo1. a resistor divider network should assu re the resulting voltage falls within the adc input range, in particular when the thermistor check function is used. adin6 adc generic input channel 6. adin6 may be used as a genera l purpose unscaled input, but in a typical application, the pa thermistor is connected here.
analog integrated circuit device data freescale semiconductor 39 mc13892 functional description functional pin description adin7 adc generic input channel 7, group 1. adin7 may be used as a general purpose unscaled input or as a divide by 2 scaled input. in a typical application, an ambient light sensor is conn ected here. a second general purpose input adin7b is available on channel 7. this input is muxed on the gpo4 pin. in the applic ation, a second ambient light sens or is supposed to be connecte d here. tsx1 and tsx2, tsy1 and tsy2 - note: the ts[xy] [12] inputs must not exceed bp or vcore. touch screen interfaces x1 and x2, y1 and y2. the touch scree n x plate is connected to tsx1 and tsx2, while the y plate is connected to y1 and y2. in inactive mode, these pins can al so be used as general purpose ad c inputs. they are respectively mapped on adc channels 4, 5, 6, and 7. in interrupt mode, a voltage is applied to the x-plate (tsx2) via a weak current source to vcore, while the y-plate is connected to ground (tsy1). tsref touch screen reference regulator. this re gulator is powered from vcore. in app lications not support ing touch screen, the tsref can be used as a low current general purpose regulator, or it can be kept disabled and the bypass capacitor omitted. adtrig adc trigger input. a rising edge on this pin will start an adc conversion. gndadc ground for a to d circuitry. thermal grounds gndsub1-9 general grounds and thermal heat sinks.
analog integrated circuit device data 40 freescale semiconductor mc13892 functional device operation programmability functional device operation programmability interfacing overview and configuration options the mc13892 contains a number of programmable registers fo r control and communication. the majority of registers are accessed through a spi interface in a typical application. th e same register set may alternatively be accessed with an i 2 c interface that is muxed on spi pins. the following t able describes the muxed pin options for the spi and i 2 c interfaces. further details for each interface mode follow in this chapter. spi interface the mc13892 contains a spi interface port, which allows access by a processor to the register set. via these registers, the resources of the ic can be controlled. the registers also provi de status information about how the ic is operating, as well as information on external signals. the spi interface pins can be reconfigured for reuse as an i 2 c interface. as a result, a conf iguration protocol mandates that the cs pin is held low during a turn on event for the ic (a weak pull-down is integrated on the cs pin. with the cs pin held lo w during startup (as would be the ca se if connected to the cs driver of an unpow ered processor, due to the integrated pull-down), the bus configuration will be latched for spi mode. the spi port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. t he addressable register map spans 64 registers of 24 data bits each. the general structure of the register set is given in the fo llowing table. bit names, positions, and basic descriptions are provided in spi bitmap . expanded bit descriptions are included in the following functional chapters for application guidance. for brevity's sake, references are occasionally made herein to the regi ster set as the ?spi map? or ? spi bits?, but note that bit a ccess is also possible through the i 2 c interface option, so such references are imp lied as generically applicable to the register set accessible by either interface. table 7. spi / i 2 c bus configuration pin name spi mode functionality i2c mode functionality cs configuration (43) , chip select configuration (44) clk spi clock scl: i 2 c bus clock miso master in, slave out (data output) sda: bi-directional serial data line mosi master out, slave in (data input) a0 address selection (45) notes 43. cs held low at cold start configures interface for spi m ode; once activated, cs functions as the spi chip select. 44. cs tied to vcore at cold start configures interface for i 2 c mode; the pin is not used in i 2 c mode other than for configuration. 45. in i 2 c mode, the mosi pin hard wired to ground or vcor e is used to select between two possible addresses. table 8. register set register register register register 0 interrupt status 0 16 unused 32 regulator mode 0 48 charger 0 1 interrupt mask 0 17 unused 33 regulator mode 1 49 usb0 2 interrupt sense 0 18 memory a 34 power miscellaneous 50 charger usb1 3 interrupt status 1 19 memory b 35 unused 51 led control 0 4 interrupt mask 1 20 rtc time 36 unused 52 led control 1 5 interrupt sense 1 21 rtc alarm 37 unused 53 led control 2 6 power up mode sense 22 rtc day 38 unused 54 led control 3 7 identification 23 rtc day alarm 39 unused 55 unused 8 unused 24 switchers 0 40 unused 56 unused 9 acc 0 25 switchers 1 41 unused 57 trim 0 10 acc 1 26 switchers 2 42 unused 58 trim 1 11 unused 27 switchers 3 43 adc 0 59 te s t 0
analog integrated circuit device data freescale semiconductor 41 mc13892 functional device operation programmability the spi interface is comprised of the package pins listed in table 9 . spi interface description the control bits are organized into 64 fields. each of these 64 fields contains 32-bits. a maximum of 24 data bits are used per field. in addition, there is one ?dead? bit between the data and address fields. the remaining bits include 6 address bits to a ddress the 64 data fields and one write enable bit to select whether the spi transaction is a read or a write. the register set will be to a large ext ent compatible with the mc13783, in order to facilitate software development. for each spi transfer, first a one is written to the read/write bi t if this spi transfer is to be a write. a zero is written to the read/ write bit if this is to be a read command only. the cs line must remain high during the entire spi transfer. to start a new spi transfer, the cs line must go inactive and then go active again. the miso line will be tri-stated while cs is low. to read a field of data, the miso pin wi ll output the data field pointed to by the 6 address bits loaded at the beginning of th e spi sequence. figure 5. spi transfer prot ocol single read/write access 12 unused 28 switchers 4 44 adc 1 60 te s t 1 13 power control 0 29 switchers 5 45 adc 2 61 te s t 2 14 power control 1 30 regulator setting 0 46 adc 3 62 te s t 3 15 power control 2 31 regulator setting 1 47 adc4 63 te s t 4 table 9. spi interface pin description spi bus description clk clock input line, data shifting occurs at the rising edge mosi serial data input line miso serial data output line cs clock enable line, active high interrupt description int interrupt to processor supply description spivcc processor spi bus supply table 8. register set register register register register
analog integrated circuit device data 42 freescale semiconductor mc13892 functional device operation programmability figure 6. spi transfer protoc ol multiple read/write access spi electrical & ti ming requirements the following diagram and table summarize the spi electrical and timing requirements. the spi input and output levels are set independently via the spivcc pin by connecting it to the de sired supply. this would typically be tied to sw4 programmed for 1.80 v. the strength of the miso driver is programmable th rough the spidrv[1:0] bits. figure 7. spi interface timing diagram
analog integrated circuit device data freescale semiconductor 43 mc13892 functional device operation programmability table 10. spi interface timing specifications parameter description t min (ns) t selsu time cs has to be high before the first rising edge of clk 15 t selhld time cs has to remain high after the last falling edge of clk 15 t sellow time cs has to remain low between two transfers 15 t clkper clock period of clk 38 t clkhigh part of the clock period where clk has to remain high 15 t clklow part of the clock period where clk has to remain low 15 t wrtsu time mosi has to be stable before the next rising edge of clk 4.0 t wrthld time mosi has to remain stable after the rising edge of clk 4.0 t rdsu time miso will be stable before the next rising edge of clk 4.0 t rdhld time miso will remain stable after the falling edge of clk 4.0 t rden time miso needs to become active after the rising edge of cs 4.0 t rddis time miso needs to become inactive after the falling edge of cs 4.0 notes 46. this table reflects a maximum spi clock frequency of 26 mhz table 11. spi interface logic io specifications parameter condition min typ max units input low cs, mosi, clk 0.0 ? 0.3*spivcc v input high cs, mosi, clk 0.7*spivcc ? spivcc+0.3 v output low miso, int output sink 100 a 0 ? 0.2 v output high miso, int output source 100 a spivcc-0.2 ? spivcc v spivcc operating range 1.75 ? 3.1 v miso rise and fall time cl = 50 pf, spivcc = 1.8 v spidrv[1:0] = 00 (default) ? 11 ? ns spidrv[1:0] = 01 ? 6.0 ? ns spidrv[1:0] = 10 ? high z ? ns spidrv[1:0] = 11 ? 22 ? ns
analog integrated circuit device data 44 freescale semiconductor mc13892 functional device operation i2c interface i 2 c interface i 2 c configuration when configured for i 2 c mode (see table 7 ) the interface may be used to access the complete register map previously described for spi access. the mc13892 can function only as an i 2 c slave device, not as a host. i 2 c interface protocol requires a device id for addressing the targ et ic on a multi-device bus. to allow flexibility in addressin g for bus conflict avoidance, pin programmable selection is provided through the mosi pin to allo w configuration for the address lsb(s). this product supports 7-bit addressing only; suppor t is not provided for 10-bit or general call addressing. the i 2 c mode of the interface is implemented generally followi ng the fast mode definition which supports up to 400 kbits/s operation. timing diagrams, electrical specificat ions, and further details can be found in the i 2 c specification. standard i 2 c protocol utilizes packets of 8-bits (bytes), with an acknowledge bit (ack) required between each byte. however, the number of bytes per transfer is unres tricted. the register map of the mc13892 is organized in 24-bit registers which corresponds to the 24-bit words supported by the spi protocol of this product. to ensure that the i 2 c operation mimics spi transactions in behavior of a complete 24-bit word being wr itten in one transaction, software is expected to perform write transactions to the device in 3 byte s equences, beginning with the msb. internally , data latching will be gated by the acknowle dge at the completion of writing the third consecutive byte. failure to complete a 3 byte write sequence will abort the i 2 c transaction and the register will re tain its previous value. this could be due to a premature stop command from the master. i 2 c read operations are also performed in byte increments se parated by an ack. read operations also begin with the msb and 3 bytes will be sent out, unless a stop command or nack is received prior to completion. the following examples show how to write and read data to th e ic. the host initiates and terminates all communication. the host sends a master command packet after driv ing the start condition. the device will re spond to the host if the master command packet contains the corresponding slave addres s. in the following examples, the device is shown always responding with an ack to transmissions from the host. if at any time a nak is rece ived, the host should terminate th e current transaction and retry t he transaction. i 2 c device id the i 2 c interface protocol requires a device id for addressing th e target ic on a multi-device bus. to allow flexibility in addressing for bus conflict avoidance, pin programmable selection is provided to allow configuration for the address lsb(s). th is product supports 7-bit addressing only. support is not provided for 10-bit or general call addressing. because the mosi pin is not utilized for i 2 c communication, it is reassigned for pin programmable address selection by hardwiring to vcore or gnd at the board level, when configured for i 2 c mode. mosi will act as bit 0 of the address. the i 2 c address assigned to fsl pm ics (shared amongst our portfolio) is as follows: 00010-a1-a0, where the a1 and a0 bits are allowed to be configur ed for either 1 or 0. it is anticipated for a maximum of two fsl pm ics on a given board, which could be sharing an i 2 c bus. the a1 address bit is internally hard wired as a ?0?, leaving the lsb a0 for board level configuration. the a1 bit will be implem ented such that it can be re- wired as a ?1? (with a metal ch ange or fuse trim), if conflicts are encounter ed before the final production material is manufactured. the designated address is def ined as: 000100-a0. i 2 c operation the i 2 c mode of the interface is implem ented, generally following the fast mode definition, which supports up to 400 kbits/s operation. the exceptions to the standard are noted to be 7- bit only addressing, and no support for general call addressing. timing diagrams, electrical s pecifications, and further de tails can be found in the i 2 c specification, which is available for download at: http://www.nxp.com/ac robat_download/literature/9398/39340011.pdf standard i 2 c protocol utilizes bytes of 8-bits, with an acknowledge bit (ack) required between each byte. however, the number of bytes per transfer are unrestricted. the register map is organized in 24-bit registers, which corresponds to the 24-b it words supported by the spi protocol of this product. to ensure that i 2 c operation mimics spi transactions in behavior of a complete 24-bit word being written in one transaction. the softwa re is expected to perform write transactions to the device in 3 byte sequences, beginning with the msb. internally, data latching will be gated by the acknowledge at the completion of writing the third consecutive byte. failure to complete a 3 byte write sequence will abort the i 2 c transaction, and the register will retain its previous value. this could be due to a premature stop comm and from the master, for example. i 2 c read operations are also performed in byte
analog integrated circuit device data freescale semiconductor 45 mc13892 functional device operation i2c interface increments separated by an ack. read operations also begi n with the msb, and 3 bytes will be sent out unless a stop command or nack is received prior to completion. the following examples show how to write and read data to th e ic. the host initiates and terminates all communication. the host sends a master command packet after driv ing the start condition. the device will re spond to the host if the master command packet contains the corresponding slave addres s. in the following examples, the device is shown always responding with an ack to transmissions from the host. if at any time a nak is rece ived, the host should terminate th e current transaction and retry t he transaction. figure 8. i 2 c 3 byte write example figure 9. i 2 c 3 byte read example
analog integrated circuit device data 46 freescale semiconductor mc13892 functional device operation i2c interface interrupt handling control the mc13892 has interr upt generation capability to inform the system on important events occurring. an interrupt is signaled to the processor by driving the int pin high. this is true whether the communication interface is configured for the spi or i 2 c. each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. e ach interrupt can be cleared by writing a 1 to the appropriate bit in the interrupt status register. this will also cause the inter rupt line to go low. if a new interrupt occurs while the processor clear s an existing interrupt bit, the interrupt line will remain high. each interrupt can be masked by setting the corresponding mask bit to a 1. as a result, when a masked interrupt bit goes high, the interrupt line will not go high. a masked interrupt can still be read from the interrupt status register. this gives the pr ocessor the option of polling for status from the ic . the ic powers up with all interrupts mask ed except the usb low-power boot, so the processor must initially poll the device to determine if any interrupts are active. alternatively, the processor can unmask the interrupt bits of interest. if a masked interrupt bit was already high, the interrupt line will go high after unmasking. the sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources . they are read only, and not latched or clearable. interrupts generated by external events are debounced, meanin g that the event needs to be stable throughout the debounce period before an interrupt is generated. bit summary table 12 summarizes all interrupt, mask, and sense bits associated with int cont rol. for more detailed behavioral descriptions, refer to the related chapters. table 12. interrupt, mask and sense bits interrupt mask sense purpose trigger debounceti me section adcdonei adcdonem ? adc has finished requested conversions l2h 0 page 100 adcbisdonei adcbisdonem ? adcbis has finished requested conversions l2h 0 page 100 tsi tsm ? touch screen wake-up dual 30ms page 100 chgdeti chgdetm chgdets chgens charger detection sense is 1 if detected charger state sense is 1 if active dual 32 ms 100 ms page 89 usbovi usbovm usbovs vbus over-voltage sense is 1 if above threshold dual 60 s page 89 chgrevi chgrevm ? charger path reverse current l2h 1.0 ms page 89 chgshorti chgshortm ? charger path short circuit l2h 1.0 ms page 89 chgfaulti chgfaultm chgfaults[1:0] charger fault detection 00 = cleared, no fault 01 = charge source fault 10 = battery fault 11 = battery temperature l2h 10 ms page 89 chgcurri chgcurrm chgcurrs charge current below threshold sense is 1 if above threshold h2l 1.0 ms page 89 cccvi cccvm cccvs cccvi transition detection dual 100 ms page 89 bponi bponm bpons bp turn on threshold detection. sense is 1 if above threshold. l2h 30 ms page 54 lobatli lobatlm lobatls low battery detect sense is 1 if below lobatl threshold l2h 0 page 54 bvalidi bvalidm bvalids usb b-session valid sense is 1 if above threshold dual l2h: 20- 24 ms h2l: 8- 12 ms page 111
analog integrated circuit device data freescale semiconductor 47 mc13892 functional device operation i2c interface additional sense bits are available to reflect the stat e of the power up mode selection pins, as summarized in table 13 . lobathi lobathm lobaths low battery warning sense is 1 if above lobath threshold. dual 30 s page 54 vbusvalidi vbusvalidm vbusvalids detects a-session valid on vbus dual l2h: 20- 24 ms h2l: 8- 12 ms page 111 idfloati idfloatm idfloats id floating detect. sense is 1 if above threshold dual 90 s page 111 idgndi idgndm idgnds usb id ground detect. sense is 1 if not to ground dual 90 s page 111 idfactoryi idfactorym idfactorys id voltage for factory mode detect sense is 1 if above threshold dual 90 s page 111 chrgse1bi chrgse1bm chrse1bs wall charger detect regulator short-circuit protection tripped dual l2h 1.0 ms 200 s page 89 scpi scps ? short circuit protection trip detection l2h 0 page 71 battdetbi battdetbm battdetbs battery removal detect dual 30 ms page 100 1hzi 1hzm ? 1.0 hz time tick l2h 0 page 49 todai todam ? time of day alarm l2h 0 page 49 pwron1i pwron1m pwron1s pwron1 event sense is 1 if pin is high. h2l 30 ms (1) page 54 l2h 30 ms page 54 pwron2i pwron2m pwron2s pwron2 event sense is 1 if pin is high. h2l 30 ms (47) page 54 l2h 30 ms page 54 pwron3i pwron3m pwron3s pwron3 event sense is 1 if pin is high. h2l 30 ms (47) page 54 l2h 30 ms page 54 sysrsti sysrstm ? system reset through pwronx pins l2h 0 page 54 wdireseti wdiresetm ? wdi silent system restart l2h 0 page 54 pci pcm ? power cut event l2h 0 page 54 warmi warmm ? warm start event l2h 0 page 54 memhldi memhldm ? memory hold event l2h 0 page 54 clki clkm clks clock source change sense is 1 if source is xtal dual 0 page 49 rtcrsti rtcrstm ? rtc reset or intrusion has occurred l2h 0 page 49 thwarnhi thwarnhm thwarnhs thermal warning higher threshold sense is 1 if above threshold dual 30 ms page 71 thwarnli thwarnlm thwarnls thermal warning lower threshold sense is 1 if above threshold dual 30 ms page 71 lpbi lpbm lpbs low-power boot interrupt dual 1.0 ms page 89 notes 47. debounce timing for the falling edge can be extended with pwronxdbnc[1:0]; refer to power control system for details. table 12. interrupt, mask and sense bits interrupt mask sense purpose trigger debounceti me section
analog integrated circuit device data 48 freescale semiconductor mc13892 functional device operation i2c interface specific registers identification the mc13892 parts can be identified though ident ification bits which are hardwired on chip. the version of the mc13892 can be identified by the icid[2:0] bits. this is used to distinguish future derivatives or customizations of the mc13892. the bits are set to icid[2:0] = 111 and are located in the revision register. the revision of the mc13892 is tracked with the revision identi fication bits rev[4:0]. the bits rev[4:3] track the full mask se t revision, where bits rev[2:0] track the metal revisions. these bits are hardwired. the bits fin[3:0] are freescale use only and are not to be explored by the application. the mc13892 die is produced using different wa fer fabrication plants. the plants can be identified via the f ab[1:0] bits. these bits are hardwired. memory registers the mc13892 has a small general purpose embedded memory of two times 24-bits to store critical data. the data is maintained when the device is turned off and when in a power cut. the contents are only reset when a rtc reset occurs, see clock generation and real time clock . table 13. additional sense bits sense description section modes[1:0] 00 = mode grounded 10 = mode to vcoredig 11 = mode to vcore page 40 pumsxs[1:0] 00 = pums grounded 01 = pums open 10 = pums to vcoredig 11 = pums to vcore page 54 chrgsss 0 = single path 1 = serial path page 89 table 14. ic revision bit assignment bits rev[4:0] ic revision 10001 pass 3.1
analog integrated circuit device data freescale semiconductor 49 mc13892 functional device operation clock generation and real time clock clock generation and real time clock clock generation the mc13892 generates a 32.768 khz clock as well as several 32.768 khz derivative clocks that are used internally for control. support is also provided for an external secure real time clock (srtc) which may be integrated on a companion system processor ic. for media prot ection in compliance with digital rights management (drm) system requirements, the clk32kmcu can be provided as a reference to the sr tc module where tamper pr otection is implemented. clocking scheme the mc13892 contains an internal 32 khz oscillator, that delivers a 32 khz nominal frequency (20%) at its outputs when an external 32.768 khz crystal is not present. if a 32.768 khz crystal is present and running, then all cont rol functions will run off the crystal derived 32 khz oscillator. in absence of a valid supply at the bp supply node (for instance due to a dead batter y), the crystal oscillator continues running, supplied from the coin cell battery until the coin cell is depleted. the 32 khz clock is driven to two output pins, clk32kmcu (intended as the ckil input to the system processor) is referenced to vsrtc, and clk32k (provided as a clock reference for the perip herals) is referenced to spivcc. the driver is enabled by the startup sequencer, and clk32kmcu is programmable fo r low-power off mode, contro lled by the state machine. additionally, a spi bit clk32kmcuen bit is provided for direct spi control. the clk32kmcuen bit defaults to a 1 and resets on rtcporb, to ensure the buffer is acti vated at the first power up and configur ed as desired for subsequent power ups. clk32k is restricted to state machine activation in normal on mode. the drive strength of the clk 32k output drivers are programmabl e with clk32kdrv[1:0] (master co ntrol bits that affect the drive strength of clk32k). during a switchover between the two clock sources (such as when the crystal oscillator is st arting up), the output clock is maintained at a stable active low or high phase of the internal 32 khz clock to avoid any clocking glitches. if the xtal clock source suddenly disappears during operation, the ic will revert ba ck to the internal clock source. given the unpredictable natu re of the event and the startup times involved, the clock may be ab sent long enough for the application to shut down during this transition, for example, due to a sag in the switchover output voltage, or absence of a signal on the clock output pins. a status bit, clks, is available to indicate to the processor which clock is currently selected: clks=0 when the internal rc is used, and clks=1 if the xtal source is used. the clki interrupt bit will be set whenever a change in the clock source occurs, and an interrupt will be generated if the corresponding clkm mask bit is cleared. oscillator specifications the crystal oscillator has been designed for use in conjunction with the micro crystal cc7v-t1a-32.768 khz-9pf-30 ppm or equivalent (such as micro crystal cc5v-t1a or epson fc135). the oscillator also accepts a clock signal from an external source . this clock signal is to be applied to the xtal1 pin, where the signal can be dc or ac coupled. a capacitive divider can be used to adapt the source signal to the xtal1 input levels. when applying an external source, the xtal2 pin is to be connected to vcoredig. the electrical characteristics of the 32 khz crystal oscillator are given in the table below, taking into account the above crystal characteristics table 15. rtc crystal specifications nominal frequency 32.768 khz make tolerance +/-30 ppm temperature stability -0.038 ppm /c 2 series resistance 80 kohm maximum drive level 1.0 w operating drive level 0.25 to 0.5 w nominal load capacitance 9.0 pf pin-to-pin capacitance 1.4 pf aging 3 ppm/year
analog integrated circuit device data 50 freescale semiconductor mc13892 functional device operation clock generation and real time clock oscillator application guidelines the guidelines below may prove to be helpful in providing a cryst al oscillator that starts reli ably and runs with minimal jitte r. pcb leakage: the rtc amplifier is a low-current circuit. ther efore, pcb leakage may signific antly change the operating point of the amplifier and even the drive level to the crystal. (cha nging the drive level to the crystal may change the aging rate, j itter, and even the frequency at a given load capa citance.) the traces should be kept as sh ort as possible to minimize the leakage, and good pcb manufacturing processes should be maintained. layout: the traces from the mc13892 to the crystal, load capaci tance, and the rtc ground are se nsitive. they must be kept as short as possible with minimal coupling to other signals. the signal ground for the rtc is to be connected to gndrtc, and via a single connection, gndrtc to the system ground. the clk32k a nd clk32kmcu square wave outpu ts must be kept away from the crystal / load capacitor leads, as the sharp edges c an couple into the circuit and lead to excessive jitter. the cryst al / load capacitance leads and the rtc ground must form a minimal loop area. crystal choice: generally speaking, crystals are not interchangeab le between manufacturers, or even different packages for a given manufacturer. if a different crystal is considered, it must be fully characterized wit h the mc13892 before it can be considered. tuning capacitors: the nominal load capacitance is 9.0 pf, therefore the tota l capacitance at each node should be 18 pf, composed out of the load capaci tance, the effective input capacitance at each pin, plus t he pcb stray capacitance for each pin. srtc support the mc13892 provides support for processors which have an integrated srtc for digital rights management (drm), by providing a vsrtc voltage to bias the srtc module of the processor, as well as a clk32k mcu at the vsrtc output level. when configured for drm mode (spi bit drm = 1), the clk32mcu driver will be kept enabled through all operational states, to ensure that the srtc module always has its reference clock. if drm = 0, the clk32kmcu driver will not be maintained in the off state. refer to table 23 for the operating behavior of the clk32kmcu output in user off, memory hold, user off wait, and internal memhold pcut modes. it is also necessary to provide a means for the processor to do an rtc initiate d wake-up of the system, if it has been programmed for such capability. this can be accomplished by co nnecting an open drain nmos driver to the pwron pin of the mc13892, so that it is in effect a parallel path for the powe r key. the mc13892 will not be able to discern the turn on event f rom a normal power key initiated turn on, but the processor should have the knowledge, since the rtc initiated turn on is generated locally. table 16. crystal oscillator main characteristics parameter condition min typ max units operating voltage oscillator and rtc block from bp 1.2 ? 4.65 v coin cell disconnect threshold at licell 1.8 ? 2.0 v rtc oscillator startup time upon application of power - ? 1.0 sec xtal1 input level external clock source 0.3 ? - v pp xtal1 input range external clock source -0.5 ? 1.2 v output low clk32k, clk32kmcu output sink 100 a 0 ? 0.2 v output high clk32k output source 100 a spivcc-0.2 ? spivcc v clk32kmcu output source 100 a vsrtc-0.2 ? vsrtc v clk32k rise and fall time cl=50 pf clk32kdrv[1:0] = 00 (default) ? 22 ? ns clk32kdrv[1:0] = 01 ? 11 ? ns clk32kdrv[1:0] = 10 ? high z ? ns clk32kdrv[1:0] = 11 ? 44 ? ns cld32kmcu rise and fall time cl=12 pf ? 22 ? ns clk32k and clk32kmcu output duty cycle crystal on xtal1, xtal2 pins 45 ? 55 %
analog integrated circuit device data freescale semiconductor 51 mc13892 functional device operation clock generation and real time clock figure 10. srtc block diagram vsrtc the vsrtc regulator provides the clk32kmcu output level. it is also used to bias the low-power srtc domain of the srtc module integrated on certain fsl processors. the vsrtc regu lator is enabled as soon as the rtcporb is detected. the vsrtc cannot be disabled. real time clock a real time clock (rtc) function is provided including time and day counters as well as an alarm function. the utilizes a 32 khz clock, either the rc oscillator or the 32.768 khz crystal oscillator as a time base, and is powered by the coin cell backup supply when bp has dropped below operational range. in configurat ions where the srtc is used, the rtc can be disabled to conserve current drain by setting the rt cdis bit to a 1 (defaults on at power up). time and day counters the 32 khz clock is divided down to a 1.0 hz time tick which drives a 17-bit time of day (tod) counter. the tod counter counts the seconds during a 24 hour period from 0 to 86,399, and will then roll over to 0. when the roll over occurs, it increm ents the 15-bit day counter. the day counter can count up to 32767 days. the 1.0 hz time tick can be used to generate a 1hzi interrupt if unmasked. table 17. vsrtc specifications parameter condition min typ max units general operating input voltage range, v inmin to v inmax valid coin cell range or valid bp 1.8 ? 3.6 v uvdet ? 4.65 v operating current load range il min to il max 0.0 ? 50 a bypass capacitor value ? 1.0 ? f active mode - dc output voltage v out v inmin < v in < v inmax il min < il < il max 1.150 1.20 1.25 v
analog integrated circuit device data 52 freescale semiconductor mc13892 functional device operation clock generation and real time clock time of day alarm a time of day alarm (toda) function can be used to turn on the application and alert the processor. if the application is already on, the processor will be interrupted. the toda and daya registers are used to set the alarm time. only a single alarm can be programmed at a time. when the tod counter is equal to th e value in toda, and the day counter is equal to the value in daya, the todai interrupt will be generated. at initial power up of the application ( application of the coin cell), the state of the toda and daya registers will be all 1's . the interrupt for the alarm (todai) is backed up by licell and will be valid at power up. if the mask bit for the tod alarm (todam) is high, then the todai interrupt is masked and the application will not turn on with the time of day alarm event (tod[16:0] = toda[16:0] and day[14:0] = daya[14:0]). by default, the todam mask bit is set to 1, thus masking the interrupt and turn on event. timer reset as long as the supply at bp is valid, the real time clock will be supplied from vcore. if not, it can be backed up from a coin cell via the licell pin. when the back up voltage drops below rtcuvdet, the rtcporb reset signal is generated and the contents of the rtc will be reset. additional registers backed up by coin cell will also reset with rtcporb. to inform the processor that the contents of the rtc are no longer valid due to the reset, a timer reset interrupt function is implemented wi th the rtcrsti bit. rtc timer calibration a clock calibration system is provided to adju st the 32,768 cycle counter that generates the 1.0 hz timer for rtc timing registers to comply with digital righ ts management specifications of 50 ppm. this calibration system can be disabled, if not needed to reduce the rtc current drain. the general implemen tation relies on the system pr ocessor to measure the 32.768 khz crystal oscillator against a higher frequency and more accurate system clock such as a tcxo. if the rtc timer needs a correction, a 5-bit 2's complement calibration word can be sent via the spi to compensate the rt c for inaccuracy in its referen ce oscillator as defined in table 18 . note that the 32.768 khz oscillator is not affected by rtccal settings. calibration is only applied to the rtc time base counter. therefore, the frequency at the clock outputs clk32k and clk32kmcu are not affected. the rtc system calibration is enabled by programming the rtccalmode[ 1:0] for desired behavior by operational mode. a slight increase in consumption will be seen when the cali bration circuitry is activated. to minimize consumption and maximize lifetime when the rtc system is ma intained by the coin cell, the rtc calibration circuitry can be automatically disabl ed when main battery contact is lost, or if it is so deeply dischar ged that rtc power draw is switched to the coin cell (configure d with rtccalmode = 01). because of the low rtc consumption, rtc accuracy can be main tained through long periods of the application being shut down, even after the main battery has dischar ged. however, it is noted that the calibr ation can only be as good as the rtccal table 18. rtc calibration settings code in rtccal[4:0] correction in counts per 32768 relative correction in ppm 01111 +15 +458 00011 +3 +92 00001 +1 +31 00000 0 0 11111 -1 -31 11101 -3 -92 10001 -15 -458 10000 -16 -488 table 19. rtc calibration enabling rtccalmode function 00 rtc calibration disabled (default) 01 rtc calibration enabled in all modes except coin cell only 10 reserved for future use. do not use. 11 rtc calibration enabled in all modes
analog integrated circuit device data freescale semiconductor 53 mc13892 functional device operation clock generation and real time clock data that has been provided, so occasional refreshing is recomm ended to ensure that any drift in fluencing environmental factors have not skewed the clock beyond desired tolerances. coin cell battery backup the licell pin provides a connection for a coin cell backup bat tery or supercap. if the main battery is deeply discharged, removed, or contact-bounced (i .e., during a power cut), the rt c system and coin cell maintained logic will switch over to the licell for backup power. this switch over occurs for a bp belo w the uvdet threshold with licell greater than bp. a small capacitor should be placed from lice ll to ground under all circumstances. upon initial insertion of the coincell, it is not immediately co nnected to the on chip circuitry. the cell gets connected when the ic powers on, or after enabling the coincell charger when the ic was already on. during operation, coincells can get damaged and their lifetime reduced when deeply discharged. in order to avoid such, the internal circuitry supplied from licell is automatically disconnected for voltages belo w the coincell disconnect threshold. the cell gets reconnected again under the same conditions as for initial insertion. the coin cell charger circuit will function as a current-limit ed voltage source, resulting in the cc/cv taper characteristic typically used for rechargeable lithium-ion batteries. the co in cell charger is enabled via the coinchen bit. the coin cell voltage is programmable through the vcoin[2:0] bits. the coin ce ll charger voltage is programmabl e in the on state where the charge current is fixed at icoinhi. if coinchen=1 when the system goes into of f or user off state, the coin cell charge r will continue to charge to the predefined voltage setting but at a lower maximum current icoinlo. this co mpensates for self discharge of the coin cell and ensures that if/when the main cell gets depleted, that the coin cell will be topped off for maximum rtc retention. the coin cell charging wi ll be stopped for the bp below uvdet. the bit coinchen itself is only cleared when an rtcporb occurs. table 20. coin cell charger voltage specifications vcoin[2:0] output voltage 000 2.50 001 2.70 010 2.80 011 2.90 100 3.00 101 3.10 110 3.20 111 3.30 table 21. coin cell charger specifications parameter typ units voltage accuracy 100 mv coin cell charge current in on and watchdog modes icoinhi 60 a coin cell charge current in off and low-power off modes (user off / memory hold) icoinlo 10 a current accuracy 30 % licell bypass capacitor 100 nf licell bypass capacitor as coin cell replacement 4.7 f licell bypass capacitor 100 nf licell bypass capacitor as coin cell replacement 4.7 f
analog integrated circuit device data 54 freescale semiconductor mc13892 functional device operation power control system power control system interface the power control system on the mc13892 inte rfaces with the processor vi a different io signals and the spi/i2c bus. it also uses on chip signals and detector outputs. table 22 gives a listing of the principal elements of this interface. table 22. power control system interface signals name type of signal function pwron1 input pin power on/off 1 button connection pwron2 input pin power on/off 2 button connection pwron3 input pin power on/off 3 button connection pwronxi/m/s spi bits pwronx pin interrupt /mask / sense bits pwron1dbnc[1:0] spi bits sets time for the pwron1 pin hardware debounce pwron2dbnc[1:0] spi bits sets time for the pwron2 pin hardware debounce pwron3dbnc[1:0] spi bits sets time for the pwron3 pin hardware debounce pwron1rsten spi bit allows for system reset through the pwron1 pin pwron2rsten spi bit allows for system reset through the pwron2 pin pwron3rsten spi bit allows for system reset through the pwron3 pin restarten spi bit allows for system restart after a pwron initiated system reset sysrsti/m spi bits pwronx system restart interrupt / mask bits wdi input pin watchdog input has to be kept high by the processor to keep the mc13892 active wdireset spi bit allows for system restart through the wdi pin wdireseti/m spi bits wdi system restart interrupt / mask bits reset output pin reset bar output (active low) to the appl ication. requires an external pull-up reset mcu output pin reset bar output (active low) to the proc essor core. requires an external pull-up pums1 input pin switchers and regulators power up sequence and defaults selection 1 pums2 input pin switchers and regulators power up sequence and defaults selection 2 standby input pin signal from primary processor to put the mc13892 in a low-power mode standbyinv spi bit standby signal polarity setting standbysec input pin signal from secondary processor to put the mc13892 in a low-power mode standbysecinv spi bit secondary standby signal polarity setting stbydly[1:0] spi bits sets delay before entering standby mode bpon threshold threshold validating turn on events bponi/m/s spi bits bp turn on threshold interrupt / mask / sense bits lobath threshold threshold for a low battery warning lobathi/m/s spi bits low battery warning interrupt / mask / sense bits lobatl threshold threshold for a low battery detect lobatli/m/s spi bits low battery detect interrupt / mask / sense bits bpsns [1:0] spi bits selects for different settings of lobatl and lobath thresholds uvdet threshold threshold for under-voltage detect ion, will shut down the device licell input pin connection for lithium based coin cell clk32kmcu output pin low frequency system clock out put for the processor 32.768 khz clk32k output pin low frequency system clock output for application (peripherals) 32.768 khz clk32kmcuen spi bit enables the clk32kmcu clock output drm spi bit keeps vsrtc and clk32kmcu active in all st ates for digital rights management, including off mode pcen spi bit enables power cut support pci/m spi bits power cut detect interrupt / mask bits pct[7:0] spi bits allowed power cut duration pccounten spi bit enables power cut counter pccount[3:0] spi bits power cut counter
analog integrated circuit device data freescale semiconductor 55 mc13892 functional device operation power control system pcmaxcnt[3:0] spi bits maximum number of allowed power cuts pcutexpb spi bit indicates a power cut timer counter expired table 22. power control system interface signals name type of signal function
analog integrated circuit device data 56 freescale semiconductor mc13892 functional device operation operating modes operating modes power control state machine figure 11 shows the flow of the power control state machine. this diagram serves as the basis for the description in the remainder of this chapter. figure 11. power control state machine flow diagram
analog integrated circuit device data freescale semiconductor 57 mc13892 functional device operation operating modes power control modes description following are text descriptions of the power states of the syste m, which give additional deta ils of the state machine, and complement figure 11 . note that the spi control is only possible in the watchdog, on, and user off wait states, and that the interrupt line int is kept low in all states except for watchdog and on. off if the supply at bp is above the uvdet threshold, only the ic core circuitry at vcoredig and the rtc module are powered, all other supplies are inactive. to exit the off mode, a valid tu rn on event is required. no specific timer is running in this mode. if the supply at bp is below t he uvdet threshold no turn on events are accepted. if a valid coin cell is present, the core gets powered from licell. the only active circui try is the rtc module, with bp greater t han uvdet detection, and the srtc support circuitry, if so configured. cold start entered upon a turn on event from off, wa rm boot, successful pcut, or silent syst em restart. the switchers and regulators are powered up sequentially to limit the inrush current. see t he power up section for sequencing and default level details. the reset signals resetb and resetbmcu are kept low. the reset time r starts running when entering a cold start. when expired, the cold start state is exit ed for the watchdog state, and both resetb a nd resetbmcu become high (o pen drain ou tput with external pull ups). the input control pins wdi, and standbyx are ignored. watchdog the system is fully powered and under spi control. reset b and resetbmcu are high. the watchdog timer starts running when entering the watchdog st ate. when expired, the system transitions to the on state, where wdi will be checked and monitored. the input control pins wdi and standbyx are ignored while in the watchdog state. on the system is fully powered and under spi control. resetb and resetbmcu are high. the wdi pin must be high to stay in this mode. the wdi io supply voltage is referenced to sp ivcc (normally connected to sw4) . spivcc must therefore remain enabled to allow for proper wdi detection. if wdi goes low, t he system will transition to the off state or cold start (dependin g on the configuration. refer to the section on si lent system restart wit h wdi event for details). user off wait the system is fully powered and und er spi control. the wdi pin no longer has control ov er the part. the wait mode is entered by a processor request for user off by setting the useroffspi bi t high. this is normally initiated by the end user via the powe r key. upon receiving the co rresponding interrupt, the system wil l determine if the product has been configured for user off or memory hold states (both of which first require passing through user off wait) or just transition to off. the wait timer starts running when entering user off wait mode. this leaves the processor time to suspend or terminate its tasks. when expired, the wait mode is exit ed for user off mode or memory hold mode, depending on warm starts being enabled or not via the warmen bit. the useroffspi bit is being reset at this po int by resetb going low. memory hold and user o ff (low-power off states) as noted in the user off wait descripti on, the system is directed into low-power off states based on a spi command in response to an intentional turn off by the end user. the only exit then will be a turn on event. to an end user, the memory hol d and user off states look like the product has been shut down co mpletely. however, a faster star tup is facilitated by maintainin g external memory in self-refresh mode (memo ry hold and user off mode) as well as powering portions of the processor core for state retention (user off only). the switcher mode control bits allow selective powering of the buck regulators for optimizing the supply behavior in the low-power off modes. linear regulators and most functional blocks are disabled (the rtc module, and turn on event detection are maintained). memory hold resetb and resetbmcu are low, and both clk32k and clk32k mcu are disabled. if drm is set, the clk32kmcu is kept active. to ensure that sw 1, sw2, and sw3 shut off in memory hold, appropriate mode settings should be used such as sw1mhmode = sw2mhmode = sw3mhmode = 0 (refer to the mode control description later in this chapter). since sw4 should be powered in pfm mode, sw4mhmode could be set to 1.
analog integrated circuit device data 58 freescale semiconductor mc13892 functional device operation operating modes any peripheral loading on sw4 should be isolated from the sw 4 output node by the pwgt2 switch, which opens in both low- power off modes due to the resetb transition. in this way, leak age is minimized from the power domain maintaining the memory subsystem. upon a turn on event, the cold start st ate is entered, the default power up values are loaded, and an the memhldi interrupt bit is set. a cold start out of the memory hold state will resu lt in shorter boot times compared to starting out of the off sta te, since software does not have to be loaded and expanded from flash. the st artup out of memory hold is also referred to as warm boot. no specific timer is running in this mode. buck regulators that are configured to stay on in memhold mode by their swxmhmode settings will not be turned off when coming out of memhold and entering a warm boot. the switchers will be reconfigured fo r their default settings as selected by the pums pin in the normal time slot that would affect them. user off resetb is low and resetbmcu is kept high. the 32 khz peripheral clock driver clk32k is disabled. clk32kmcu (connected to the processor's ckil input) is maintained in th is mode if the clk32kmcuen and useroffclk bits are both set, or if drm is set. the memory domain is held up by setting sw4uomode = 1. similarly, the sw1, and/or sw2, and/or sw3 supply domains can be configured for swxuomode = 1 to keep them powered through the user off event. if one of the switchers can be shut down on in user off, its mode bits would typically be set to 0. any peripheral loading on sw1 and/or sw2 should be isolated from the output node( s) by the pwgt1 switch, which opens in both low-power off modes due to the resetb transition. in th is way, leakage is minimized from the power domain maintaining the processor core. since power is maintained for the core (which is put into it s lowest power state) and sinc e mcu resetbmcu does not trip, the processor's state may be quickly recovered when exiting useroff upon a turn on event. the clk32kmcu clock can be used for very low frequency / low-power idling of the core(s), minimizing battery drain while allowing a rapid recovery from wh ere the system left off before the useroff command. upon a turn on event, warm start state is entered, and the default power up values are loaded. a warm start out of user off will result in an almost instantaneous start up of the system, since the internal states of the processor were preserved along w ith external memory. no specific ti mer is running in this mode. warm start entered upon a turn on event from user off. the switchers and regulators are powered up sequentially to limit the inrush current; see the power up section for sequencing and default leve l details. if sw1, sw2, sw3, and/or sw4 were configured to stay on in user off mode, they will not be turned off when coming out of user off and entering a warm start. the buck regulator s will be reconfigured for their default settings as selected by the pums pin in the respective time slot defined in the sequence r selection. resetb is kept low and resetbmcu is kept high. clk32kmcu is kept active if enabl ed via the spi. the reset timer starts running when entering warm start. when expir ed, the warm start state is exited for the watchdog state, a warmi interrupt is generated, and resetb will go high. internal memhold power cut refer to the next section for details about powe r cuts and the associated state machine response. power cut description when the supply at bp drops below the uvdet threshold due to battery bounce or battery removal, the internal memhold power cut mode is entered and a power cut (pcut) timer starts running. the backup coin cell will now supply the rtc as well as the on chip memory registers and some other power control related bits. all other supplies will be disabled. the maximum duration of a power cut is determined by the pcut timer pct[7:0] preset via spi. when a pcut occurs, the pcut timer will internally be decremented ti ll it expires, meaning counted down to zero . the contents of pct[7:0] does not refl ect the actual count down value but will keep the programmed valu e and therefore does not have to be reprogrammed after each power cut. if power is not reestablished above bpon before the pcut time r expires, the state machine tr ansitions to the off mode at expiration of the counte r, and clears the pcutexb bit by setting it to 0. this transition is re ferred to as an ?unsuccessful? p cut. upon re-application of power before expira tion (an ?successful pcut?, defined as bp first rising above the uvdet threshold and then above the bpon threshold before the p cut timer expires), a cold start is engaged.
analog integrated circuit device data freescale semiconductor 59 mc13892 functional device operation operating modes in order to distinguish a non-pcut initia ted cold start from a cold start after a pcut, the pci interrupt should be checked by software. the pci interrupt is cleared by software or when cycling through the off state. because the pcut system quickly disables all of the power tree, the battery voltage may recover to a level with the appearance of a valid supply once the battery is unloaded. however, upon a restart of th e ic and power sequencer, the surge of current through the battery and trace imped ances can once again cause the bp node to drop below uvdet. this chain of cyclic power down / power up sequences is referr ed to as ?ambulance mode?, and the power control system includes strategies to minimize the chance of a product falling into and getting stuck in ambulance mode. first, the successful recovery out of a pcut requires the bp no de to rise above bpon, providi ng hysteretic margin from the uvdet threshold. secondly, the number of times the pcut mo de is entered is counted with the counter pccount[3:0], and the allowed count is limited to pcmaxcnt[3:0] set through th e spi. when the contents of both become equal, then the next pcut will not be supported and the system will go to off mode. after a successful power up after a pcut (i.e., valid power is reestablished, the system comes out of reset, and the processor reassumes control), software should clea r the pccount[3:0] counter. counting of pcut events is enabled via the pccounten bit. this mode is only supported if the power cu t mode feature is enabled by setting the pcen bit. when not enabled, in case of a power failure, the state machine will trans ition to the off state. spi cont rol is not possible during a p cut event and the interrupt line is kept low. spi configuration fo r pcut support should also in clude setting the pcutexpb=1 (see the silent restart from pcut event section later in this chapter). internal memhold power cut as described above, a momentary power interruption will put the sy stem into the internal memhold power cut state if pcuts are enabled. the backup coin cell will now supply the mc13892 core along with the 32 khz crystal oscillator, the rtc system and coin cell backed up registers. all regulat ors and switchers will be shut down to preserve the coin cell and rtc as long as possible. both resetb and resetbmcu are tripped, bringing the entire system down along with the supplies and external clock drivers, so the only recovery out of a power cut state is to reestablish power and initiate a cold start. if the pct timer expires before po wer is reestablished, the system transitions to the off state and awai ts a sufficient supply recovery. silent restart from pcut event if a short duration power cut event occurs (such as from a batt ery bounce, for example), it may be desirable to perform a silen t restart, so the system is re-initialized wit hout alerting the user. this can be configured by setting t he pcutexpb bit to a ?1? at booting or after a cold start. this bit resets on rtcporb, ther efore any subsequent cold start can first check the status of pcutexpb and the pci bit. the pcutexpb is cleared to ?0? when tr ansitioning from pcut to off. if there was a pcut interrupt and pcutexpb is still a ?1?, then the state machine has not transitioned through off, which c onfirms that the pct timer has not expired during the pcut event (i.e., a successful power cut). in case of a successful power cut, a silent restart may be appropriate. if pcutexpb is found to be a ?0? after the cold start where pci is found to be a ?1?, then it is inferred that the pct timer ha s expired before power was reestablished, flagging an unsuccessful power cut or first power up, so the startup user greeting may be desirable for playback. silent system restart with wdi event a mechanism is provided for recovery if the system software somehow gets into an abnormal st ate which requires a system reset, but it is desired to make the reset a silent event so as to happen without end user awareness. the default response to w di going low is for the state machine to tr ansition to the off state (when wdireset = 0). however, if wdireset = 1, the state machine will go to cold start without passing through off mode a wdireset event will generate a maskable wdireseti interrupt and also increment the pccount counter. this function is unrelated to pcuts, but it s hares the pcut counter so that the number of silent system restarts can be limited by the programmable pcmaxcnt counter. when pcut support is used, the software should set the pcutexpb bit to ?1?. since this bit resets with rtcporb, it will not be reset to ?0? if a wdi falls and the state machine goes straight to the cold start state. ther efore, upon a restart, the soft ware can detect a silent system restart, if there is a wdireseti interrupt and pcutexpb = 1. the application may then determine that an inconspicuous restart without showing may be mo re appropriate than launching into the welcoming routine. a pcut event does not trip the wdireseti bit.
analog integrated circuit device data 60 freescale semiconductor mc13892 functional device operation operating modes global system restart a global system reset can be enabled through the glbrsten b spi bit. the global reset on the mc13892a/c versions is active low so it is enabled when the glbrstenb = 0. in the mc13892 b/d versions global reset is active high and it is enabled when the glbrstenb = 1. when gl obal reset is enabled and the pwron3 button is held for 12 seconds, the system will reset and the following actions will take place: ? power down ? disable the charger ? reset all the registers incl uding the rtcporb registers ? power back up after the difference between the 12 sec timer, and when the user releases the button as the power off time (for example, if the power button was held for 12.1 s, then the time that the ic would be off would be only 100 ms) if pwron3 is held low for less than 12 seconds, it will act as a normal pwron pin. this feature is enabled by default in the mc13892a/c versions, and disabled by default in the mc13892b/d versions. clk32kmcu clock driver control through states as described previously, the clocking behavior is influenced by the state machine is in and the setting of the clocking related spi bits. a summary is given in table 23 for the clock output clk32kmcu. turn on events when in off mode, the mc13892 can be powered on via a turn on event. the turn on events are listed in table 24 . to indicate to the processor what event caused the system to power on , an interrupt bit is associated with each of the turn on events. masking the interrupts related to the turn on events will no t prevent the part to turn on, except for the time of day a larm. power button press pwron1, pwron2, or pwron3 pulled low with correspondi ng interrupts and sense bits pwron1i, pwron2i, or pwron3i, and pwron1s, pwron2s, or pwron3s. a power on/off button is c onnected here. the pwronx can be hardware debounced through a programmable debouncer pwronxdb nc[1:0] to avoid the application to power up upon a very short key press. in addition, a software debounce can be applied. bp should be above uvdet. the pwronxi interrupt is generated for both the falling and the rising edge of the pwronx pin. by default, a 30 ms interrupt debounce is applied to both falling and rising edges. the falling edge debounce timing can be extended with pwronxdbnc[1:0] as defined in the following table. the pwronxi interrupt is cleared by so ftware or when cycling through the off mode. table 23. clk32mcu control logic table mode drm clk32kmcuen useroffclk clock output clk32kmcu off, memory hold, internal memhold pcut 0 x x disabled 1 x x enabled on, cold start, warm start, watchdog, user off wait 0 0 x disabled 1 x x enabled 0 1 x enabled user off 0 x 0 disabled 1 x x enabled 0 1 1 table 24. pwronx hardware debounce bit settings bits state turn on debounce (ms) falling edge int debounce (ms) rising edge int debounce (ms) pwronxdbnc[1:0] 00 0 31.25 31.25 01 31.25 31.25 31.25 10 125 125 31.25 11 750 750 31.25 notes 48. the sense bit pwronxs is not debounced and follows the state of the pwronx pin
analog integrated circuit device data freescale semiconductor 61 mc13892 functional device operation operating modes charger attach chrgraw is pulled high with corresponding interrupt and sense bits chgdeti and chgdets. this is equivalent to plugging in a charger. bp should be above bpon. the charger tu rn on event is dependent on the charge mode selected. for details on the charger detection and turn on, see battery interface and control . battery attach bp crossing the bpon threshold which corre sponds to attaching a charged battery to the product. a corresponding bponi interrupt is generated, which can be cleared by software or when cycling through the off mode. note that bponi is also generated after a successful power cut and potentially when applying a charger. usb attach vbus pulled high with corresponding interrupt and sense bits bva lidi and bvalids. this is equivalent to plugging in a usb cable. bp should be above bpon and the battery voltage above batton. for de tails on the usb detection, see connectivity . rtc alarm tod and day become equal to the alarm setting programmed. this allows powering up a product at a preset time. bp should be above bpon. for details and related interrupts, see clock generation and real time clock . system restart system restart may occur after a system reset. this is an optional function, see also the following turn off events section. bp should be above bpon. turn off events power button press user shut down of a product is typically done by pressing the power button connect ed to the pwronx pin. this will generate an interrupt (pwronxi), but will not directly power off the part. t he product is powered off by the processor's response to thi s interrupt, which will be to pull wdi low. pressing the power butt on is therefore under normal circ umstances not considered as a turn off event for the state machine. note that software can configure a user initiated power down via a power button press for transition to a low-power off mode (memory hold or user off) for a quicker restar t than the default transit ion into the off state. power button system reset a secondary application of the pwron pin is the option to generate a system reset. th is is recognized as a turn off event. by default, the system reset function is di sabled but can be enabled by setting the pwronxrsten bits. when e nabled, a 4 second long press on the power button will cause the device to go to the off mode and as a result the entire application will p ower down. an sysrsti interrupt is generated upon the next power up. alternatively, the system can be configured to restart automatically by setting the restarten bit. thermal protection if the die gets overheated, the thermal protection will power off the part to avoid damage. a turn on event will not be accepte d while the thermal protection is still being tr ipped. the part will remain in off mode un til cooling sufficiently to accept a tu rn on event. there are no specific interrupts related to this other than the warning interrupts. under-voltage detection when the voltage at bp drops below the under-voltage detection threshold uvdet, the state machine will transition to off mode if pcut is not enabled, or if t he pct timer expires when pcut is enabled. timers the different timers as used by the state machine are in table 25 . this listing does not include rtc timers for timekeeping. a synchronization error of up to one cl ock period may occur with respect to the occurrence of an asynchronous event. the duration listed below is therefore the effective minimum time period.
analog integrated circuit device data 62 freescale semiconductor mc13892 functional device operation operating modes timing diagrams a turn on event timing diagram example shows in figure 12 . figure 12. power up timing diagram power up at power up, switchers and regulators are se quentially enabled in time slots of 2.0 ms steps to limit the in rush current after an initial delay of 8.0 ms, in which the core circuitry gets enabled. to ensu re a proper power up sequence, the outputs of the switchers are discharged at the beginning of a cold start. for that reason, an 8.0 ms delay allows the outputs of the linear regulators to be fully discharged as well through the built-in di scharge path. time slots which include multiple regulator star tups will be sub-sequenced for additional inrush balancing. the peak inrush current per event is li mited. any under-voltage detectio n at bp is masked while the power up sequencer is running. the power up mode select pins (pums1 and 2) are used to conf igure the startup characteristi cs of the regulators. supply enabling and output level options are sele cted by hardwiring the pumsx pins for the desired configuration. the state of the pumsx pins can be read out via the sense bits pumssxx[1:0]. ty ing the pumsx pins to ground corresponds to 00, open to 01, vcoredig to 10, and vcore to 11. the recommended power up strategy for end products is to bring up as little of the system as possible at booting, essentially sequestering just the bare essentials, to allow processor startup and software to run. with such a strategy, the startup transi ents are controlled at lower levels, an d the rest of the system power tree can be brought up by software. this allows optimization o f supply ordering where specific sequences ma y be required, as well as supply default va lues. software code can load up all of the required programmable options to avoid sneak paths, under/o ver-voltage issues, startup sur ges, etc., without any change in hardware. for this reason, the power gate dr ivers are limited to activation by software rather than the sequencer, allowing the core(s) to startup before any pe ripheral loading is introduced. the power up defaults table 26 shows the initial setup for the voltage level of the switchers and regulators, and whether they get enabled. table 25. timer main characteristics timer duration under-voltage timer 4.0 ms reset timer 40 ms watchdog timer 128 ms power cut timer programmable 0 to 8 seconds in 31.25 ms steps
analog integrated circuit device data freescale semiconductor 63 mc13892 functional device operation operating modes the power up sequence is shown in table 27 . vcoredig, vsrtc, and vcore are brought up in the pre-sequencer startup. once vcoredig is activated (i.e., at the first-time power application), it will be continuously powered as long as a valid coin cell is present. table 26. power up defaults table i.mx 37/51 37/51 37/51 37/51 35 27/31 pums1 gnd open vcoredig vcore gnd open pums2openopenopenopen gnd gnd sw1 (49) 0.775 1.050 1.050 0.775 1.200 1.200 sw2 (49) 1.025 1.225 1.225 1.025 1.350 1.450 sw3 (49) 1.200 1.200 1.200 1.200 1.800 1.800 sw4 (49) 1.800 1.800 1.800 1.800 1.800 1.800 swbst off off off off 5.000 5.000 vusb 3.300 (50) 3.300 (50) 3.300 (50) 3.300 (50) 3.300 (52) 3.300 (52) vusb2 2.600 2.600 2.600 2.600 2.600 2.600 vpll 1.800 1.800 1.800 1.800 1.500 1.500 vdig 1.250 1.250 1.250 1.250 1.250 1.250 viohi 2.775 2.775 2.775 2.775 2.775 2.775 vgen2 3.150 off 3.150 off 3.150 3.150 vsd off off off off 3.150 3.150 notes 49. the switchers swx are activated in pwm pulse skipping mode, but allow ed when enabled by the startup sequencer. 50. usb supply vusb, is only enabled if 5.0 v is present on uvbus. 51. the following supplies are not included in the matrix since they are not intended for activation by the startup sequencer: v cam, vgen1, vgen3, vvideo, and vaudio 52. swbst = 5.0 v powers up and does vusb regardless of 5.0 v present on uvbus. by default vusb will be supplied by swbst. table 27. power up sequence tap x 2ms pums2 = open (i.mx37, i.mx51) pums2 = gnd (i.mx35, i.mx27) 0 sw2 sw2 1 sw4 vgen2 2 viohi sw4 3 vgen2 viohi, vsd 4 sw1 swbst, vusb (56) 5 sw3 sw1 6 vpll vpll 7 vdig sw3 8 - vdig 9 vusb (55) , vusb2 vusb2 notes 53. time slots may be included for blocks which are defined by t he pums pin as disabled to allow for potential activation. 54. the following supplies are not included in the matrix since they are not intended fo r activation by the startup sequencer: v cam, vgen1, vgen3, vvideo, and vaudio . swbst is not included on the pums2 = open column. 55. usb supply vusb, is only enabled if 5.0 v is present on uvbus. 56. swbst = 5.0 v powers up and so does vusb regardless of 5.0 v present on uvbus. by default vusb will be supplied by swbst.
analog integrated circuit device data 64 freescale semiconductor mc13892 functional device operation operating modes power monitoring the voltage at bpsns and bp is monitored by detectors as summarized in table 28 . the uvdet and bpon thresholds are relat ed to the power on/off events as described earlier in this chapter. the lobath threshold is used as a weak battery warning. an interrupt lobat hi is generated when crossing the threshold (dual edge). the lobatl threshold is used as a low battery detect. an interrupt lobatli is generated when dro pping below the threshold. the sense bits are coded in line with previous generation parts. power saving system standby a product may be designed to go into dsm after periods of inacti vity, such as if a music player completes a play list and no further activity is detected, or if a gami ng interface sits idle for an extended perio d. two standby pins are provided for boar d level control of timing in and out of such deep sleep modes. when a product is in dsm it may be able to reduce the over all platform current by loweri ng the switcher output voltage, disabling some regulators, or forcing some gpo low. this can be obtained by spi configuration of the standby response of the circuits along with cont rol of the standby pins. to ensure that shared resources are properly powered when requir ed, the system will only be allowed into standby when both the standby and the standbysec are activat ed. the states of the stan dby pins only have influence in on mode. a command to transition to one of the low-power off states (user off or memory hold , initiated with useroffspi = 1) has priority over standby. note that the standby pins are programmabl e for active high or active low polarity, and that decoding of a standby event will take into account the programmed input polarities associated with each pin. table 28. bp detection thresholds threshold in v bit setting falling edge rising edge bpsns1 bpsns0 uvdet lobatl lobath bpon 0 0 2.55 2.8 3.0 3.2 0 1 2.55 2.9 3.1 3.2 1 0 2.55 3.0 3.3 3.2 1 1 2.55 3.1 3.4 3.2 notes 57. default setting for bpsns[1:0] is 00. the above specified thresholds are 50 mv accurate for the indicated edge. a hysteresis is applied to the detectors on the order of 100 mv. bpon is monitoring bp. uvdet, lobatl and lobath are monitoring bpsns and thresholds are correlated. table 29. power monitoring summary bpsns bpons lobaths lobatls < lobatl 0 0 1 lobatl-lobath 0 0 0 lobath-bpon 0 1 0 >bpon 1 1 0 table 30. standby pin and polarity control standby (pin) standbyinv (spi bit) standbysec (pin) standbysecinv (spi bit) standby control (58) 0 0 x x 0 x x 0 0 0 1 1 x x 0 x x 1 1 0 0 1 0 1 1
analog integrated circuit device data freescale semiconductor 65 mc13892 functional device operation operating modes when requesting standby, a programmable delay (stbydly) of 0 to 3 clock cycles of the 32 khz clock is applied before actually going into standby (i.e. before turning off some supplies). no delay is appli ed when coming out of standby. regulator mode control the regulators with embedded pass devices (vdig, vpll, viohi, vusb, vusb2, and vaudio) have an adaptive biasing scheme, thus, there are no distinct oper ating modes such as a normal mode and a low-power mode. therefore, no specific control is required to put these regulators in a low-power mode. the regulators with external pass devices (vsd, vvideo, vgen 1, and vgen2) can also operate in a normal and low-power mode. however, since a load curr ent detection cannot be performed for these regulators, the transition between both modes is not automatic and is controlled by se tting the corresponding mode bits for the operational behavior desired. the regulators vgen3 and vcam can be co nfigured for using the internal pass devic e or external pass device as explained in power control system . for both configurations, the transition between no rmal and low-power modes is controlled by setting the vxmode bit for the specific regulator . therefore, depending on th e configuration selected, t he automatic low-power mode is available. the regulators can be disabled and the general purpose outputs can be forced low when going into standby as described previously. each regulator and gpo has an associated spi bit for this. when the bit is not set, standby is of no influence. the actual operating mode of the regulators as a function of standby is not reflected th rough the spi. in other words, the spi will read back what is programm ed, not the actual state. for regulators with internal pass devices and genera l outputs, the previous table can be simplified. 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 notes 58. standby = 0: system is not in standby; standby = 1: system is in standby and st andby programmability is activated. table 31. delay of standby- initiated response stbydly[1:0] function (1) 00 no delay 01 one 32 k period (default) 10 two 32 k periods 11 three 32 k periods table 32. ldo regulator control (external pass device ldos) vxen vxmode vxstby standby regulator vx 0 x x x off 1 0 0 x on 1 1 0 x low-power 1 x 1 0 on 1 0 1 1 off 1 1 1 1 low-power notes 59. this table is valid for regulat ors with an external pass device 60. standby refers to a standby event as described earlier table 30. standby pin and polarity control standby (pin) standbyinv (spi bit) standbysec (pin) standbysecinv (spi bit) standby control (58)
analog integrated circuit device data 66 freescale semiconductor mc13892 functional device operation operating modes buck regulators operational modes of the buck regulators c an be controlled by direct spi programming , altered by the state of the standby pins, by direct state machine influence, or by load current magnitude when so configured. available modes include pwm with no pulse skipping (pwm), pwm with pulse skipping (pwmps), pulse frequency mode (pfm), and off. the transition between the two modes pwmps and pfm can occur automat ically, based on the load current. ther efore, no specific control is required to put the switchers in a low-power mode. when the buck regulato rs are not configured in the auto mode, power savings may be achieved by disabling switchers when not needed, or running them in pfm m ode if loading conditions are light enough. sw1, sw2, sw3, and sw4 can be configured for mode switchi ng with standby or autonomously based on load current with adaptive mode control (auto). additiona lly, provisions are made for maintaining pfm operation in useroff and memhold modes to support state retention for faster startup from the low-power off modes for warm start or warm boot. table 34 summarizes the buck regulator progra mmability for normal and standby modes. in addition to controlling the operating mode in standby, th e voltage setting can be changed. the transition in voltage is handled in a controlled slope manner, see supplies , for details. each switcher has an associated set of spi bits for standby mode set points. by default the standby settings are identical to th e non-standby settings, which ar e initially defined by pums programming. the actual operating mode of t he switchers as a function of standby pins is not reflected through the spi. the spi will read back what is programmed in swxmode[3: 0], not the actual state that may be altered as described previously. table 35 and table 36 show the switcher mode control in the low-power off states. note th at a low-power off activated swx should use the standby set point as programmed by swxstby[4: 0]. the activated switcher(s) will maintain settings for mode and voltage until the next startup event. when the respective time slot of the st artup sequencer is reached for a given switche r, its mode and voltage settings will be updated the same as if starting out of the off st ate (except that switchers active throug h a low-power off mode will not be off when the startup sequenc er is started). table 33. ldo regulator control (internal pass device ldos) vxen vxstby standby regulator vx 0 x x off 1 0 x on 1 1 0 on 1 1 1 off notes 61. this table is valid for regulat ors with an internal pass device 62. standby refers to a standby event as described earlier table 34. switcher mode control for normal and standby operation swxmode[3:0] normal mode (63) standby mode (63) 0000 off off 0001 pwm off 0010 pwmps off 0011 pfm off 0100 auto off 0101 pwm pwm 0110 pwm auto 0111 na na 1000 auto auto 1001 pwm pwmps 1010 pwmps pwmps 1011 pwmps auto 1100 auto pfm 1101 pwm pfm 1110 pwmps pfm 1111 pfm pfm notes 63. standby defined as logical and of standby and standbysec pin
analog integrated circuit device data freescale semiconductor 67 mc13892 functional device operation operating modes power gating system the low-power off states are provided to allow faster system booting from two ps eudo off conditions: memory hold, which keeps the external memory powered for self refresh, and user off, which keeps the processor powered up for state retention. for reduced current drain in low-power o ff states, parts of the system can benefit from power gating to isolate the minimum essentials for such operational modes. it is also necessary to ensure that the power budget on backed up domains are within the capabilities of switchers in pfm mode. an additional benefit of power gating peripheral loads du ring system startup is to enabl e the processor core to complete booting, and begin running software before additional supplies or peripheral devices are powered . this allows system software to bring up th e additional supplies and close power gating switches in the most optimum order, to avoid problems with supply sequencing or transient current surg es. the power gating switch dr ivers and integrated control are included for optimizin g the system power tree. the power gate drivers could be used for other general power gati ng as well. the text herein assumes the standard application of pwgt1 for core supply power gating and pwgt2 for memory hold power gating. user off power gating user off configuration maintains pfm mode switchers on both the processor and external memory power domains. pwgtdrv1 is provided for power gating peripheral loads sharin g the processor core supply dom ain(s) sw1, and/or sw2, and/ or sw3. in addition, pwgtdrv2 is provided support to power gate peripheral loads on the sw4 supply domain. in the typical application, sw1, sw2, and sw3 will all be kept active for the proce ssor modules in state retention, and sw4 retained for the external memory in self refresh mode. sw1, sw2, and sw3 power gating fet drive would typically be connected to pwgtdrv1 (for parallel nmos switches); sw4 power gating fet drive would typically be connected to pwgtdrv2. when low-power off mode is activated, the powe r gate drive circuitry will be disabled, turn ing off the nmos power gate switches to isolate the maintained supply domains from any peripheral loading. the power gate switch driver consist of a fully integrated charge pump (~5.0 v) which provides a low-power output to drive the gates of external nmos switches placed between power sources and peripheral loading. the processor core(s) would typically be connected directly to the sw1 out put node so that it can be ma intained by sw1, while any circuitry that is not ess ential for booting or user off op eration is decoupled via the power gate switch. if multiple power domains are to be controlled togeth er, power gating nmos switches can share the pwgt1 gate drive. however, extra gate ca pacitance may require additional time for the charge pump gate drive voltage to reac h its full value for minimum switch rds_on. table 35. switcher control in memory hold swxmhmode memory hold operational mode (64) 0 off 1 pfm notes 64. for memory hold mode, an activated swx should use the standby set point as programmed by swxstby[4:0]. table 36. switcher control in user off swxuomode user off operational mode (65) 0 off 1 pfm notes 65. for user off mode, an activated swx shoul d use the standby set point as programmed by swxstby[4:0].
analog integrated circuit device data 68 freescale semiconductor mc13892 functional device operation operating modes figure 13. power gating diagram memory hold power gating as with the user off power gating strategy described previously , memory hold power gating is intended to allow isolation of the sw4 power domain, to selected circuitry in low-power modes while cutting off the switcher domain from other peripheral loads. the only difference is that processor supplies sw1, and/or sw2, and/or sw3, are shut down in memory hold, so just the external memory is maintained in self refresh mode. an external nmos is to be placed between the direct-conne cted memory supply and any peripheral loading. the pwgtdrv2 pin controls the gate of the external nmos and is normally pulled up to a charge pumped voltage (~5.0 v). during memory hold or user off, pwgtdrv2 will go low to turn off the nmos switch and isolate memory on the sw4 power domain. figure 14. memo ry hold circuit exiting from low-power off modes when a turn on event occurs, any switchers that are active through low-power off modes will stay in pfm mode at their standby voltage set points until the applicable time slot of the startup sequencer. at that point, the respective switcher is u pdated for the pumsx defined default state for mode and voltage. subseq uent closing of the power gate switches will be coordinated by software to comple te restoration of the full system power tree.
analog integrated circuit device data freescale semiconductor 69 mc13892 functional device operation operating modes power gating specifi cations and control a power gate driver pulled low may be thought of as power gating being active since this is the condition where a power source is isolated (or power gated) from its loading on the other si de of the switch. the power gate drive outputs are spi controlled in the active modes as shown in table 38 . when spi controlled (watchdog, on, and us er off wait states), the pwgtdrvx power gate drive pin states are determined by spi enable bits pwgtxspien, according to table 39 . general purpose outputs gpo drivers included can provide useful system level signa ling with spi enabling and programmable standby control. key use cases for gpo outputs include battery pack thermistor biasing a nd enabling of peripheral devices, such as light sensor(s), camera flash, or even supplemental regulators. spi enabling can be used for coordinating gpos with adc c onversions for consumption efficiency and desired settling characteristics. four general purpose outputs are provided, summarized in table 40 and table 41 (active high polarities assumed). table 37. power gating characteristics parameter condition min typ max units output voltage v out output high 5.0 5.40 5.70 v output low ? ? 100 mv turn-on time (66) , (67) enable to v out = v outmin -250 mv ? 50 100 s turn off time disable to v out < 1.0 v ? ? 1.0 s average bias current t > 500 s after enable ? 1.0 5.0 a pwgtx input voltage nmos drain voltage 0.6 ? 2.0 v dc load current at pwgtdrvx output ? ? 100 na load capacitance (66) used as a condition for the other parameters 0.5 ? 1.0 nf notes 66. larger capacitive loading values will l ead to longer turn on times exceeding the giv en limits; smaller values will lead to l arger ripple at the output. 67. input supply is assumed in the range of 3.0 < bp < 4.65 v; lower bp values may extend turn on time, and functionality not supported for bp less than ~2.7 v. table 38. power gate drive state control mode pwgtdrv1 pwgtdrv2 off l ow low cold start low low warm start low low watchdog, on, user off wait spi controlled spi controlled user off, memory hold, internal memory hold power cut low low table 39. power gating logic table pwgtxspien pwgtdrvx 1 low 0 high notes 68. applicable for watchdog, on and user off wait modes only. if pwgt1spien and pwgt2spien both = 1 then the charge pump is disabled.
analog integrated circuit device data 70 freescale semiconductor mc13892 functional device operation operating modes the gpo1 output is intended to be used for battery thermistor bi asing. for accurate thermistor reading by the adc, the output resistance of the gpo1 driv er is of importance; see adc subsystem . finally, a muxing option is included to allow gpo4 to be co nfigured for a muxed connection into channel 7 of the gp adc. as an application example, for a dual light sensor applic ation, channel 7 can be toggled between the adin7 (adinsel7 = 00) and gpo4 (adinsel7 = 11) for convenient connectivity and monitoring of two sensors. the gpo4 pin is configured for adc input mode by default (gpo4adin = 1) so that the gpo driver stage is high- impedance at power up. the gpo4 pin can be configured by software for gpo operation with gpo4adin = 0. refer to adc subsystem for gp adc details. table 40. gpo control bits spi bit gpo control gpoxen gpox enable gpoxstby gpox controlled by standby x = 1, 2, 3, or 4 table 41. gpo control scheme gpoxen gpoxstby standby output gpox 0 x x low 1 0 x high 1 1 0 high 1 1 1 low notes 69. gpo1 is automatically made active high when a charger is detected, see battery interface and control for more information. table 42. gpo1 driver output characteristics parameter condition min typ max units gpo1 output impedance output vcore impedance to vcore 200 ? 500 ohm
analog integrated circuit device data freescale semiconductor 71 mc13892 functional device operation supplies supplies supply flow the switched mode power supplies and the linear regulators are dimensioned to support a supply flow based upon figure 15 . figure 15. supply distribution while maintaining the performance as specified, the mi nimum operating voltage for the supply tree is 3.0 v. for lower voltages, the performance may be degraded. table 43 summarizes the available power supplies. table 43. power tree summary supply purpose (typical application) output voltage (in v) load capability (in ma) sw1 buck regulators for processor core(s) 0.600-1.375 1050 sw2 buck regulators for processor sog, etc. 0.600-1.375; 1.100-1.850 800 sw3 buck regulators for internal processor memory and peripherals 0.600-1.375; 1.100-1.850 800 sw4 buck regulators for external memory and peripherals 0.600-1.375; 1.100-1.850 800 swbst boost regulator for usb otg, tri-color led drivers 5.0 300 viohi io and peripheral supply, efuse support 2.775 100 vpll quiet analog supply (pll, gps) 1.2/1.25/1.5/1.8 50 vdig low voltage digital (dpll, gps) 1.05/1.25/1.65/1.8 50 vsd sd card, external pnp 1.8/2.0/2.6/2.7/2.8/2.9/3.0/3.15 250 vusb2 external usb phy supply 2.4/2.6/2.7/2.775 50 vvideo tv dac supply, external pnp 2.5/2.6/2.7/2.775 350 vaudio audio supply 2.3/2.5/2.775/3.0 150 charger protect and detect swbst 5.0v coincell cc charge rtc, mema/b sw1 gp core dvs domain external memory viohi vcore vcam core sd, tflash camera io and digital peripherals io, efuse gpos 0.6 to 1.15v vgen3 peripherals vsd vpll core plls (analog) battery voltage & current control bp power audio coin cell peripherals sw4 1.8v sw2 0.6 to 1.25v pgate vdig gps core vgen1 wlan, bt vgen2 mlc nand alternate hardwired bias option from external 2.2v switcher vcoredig processor interfaces pnp pnp pnp pnp serial backlight drivers system supplies external loads internal loads energy source legend sog core dvs domain sw3 1.25v internal processor memory pnp pnp accessory usb cable interface uvbus vvideo pnp vaudio audio tv-dac pnp vusb usb phy pgate peripherals vusb2 alternate hardwired bias option from sw4
analog integrated circuit device data 72 freescale semiconductor mc13892 functional device operation supplies buck regulator supplies four buck regulators are provided with inte grated power switches and synchronous rectif ication. in a typical application, sw1 and sw2 are used for supplying the application processor core power domains. split power domains allow independent dvs control for processor power optim ization, or to support technologies with a mix of device types with different voltage ratings. sw3 is used for powering internal processor memory as well as low voltage peripheral devices and interfaces which can run at the same voltage level. sw4 is used for powering external memory as well as low voltage peripheral devices and interfaces which can run at the same voltage level. an anticipated platform use case applies sw1 and sw2 to proc essor power domains that require voltage alignment to allow direct interfacing without band width limiting synchronizers. the buck regulators have to be supplied from the system supply bp, which is drawn from the main battery or the battery charger (when present). figure 16 shows a high level block diagram of the buck regulators. figure 16. buck regulator architecture vcam camera supply, internal pmos 2.5/2.6/2.75/3.0 65 camera supply, external pnp 2.5/2.6/2.75/3.0 250 vgen1 general peripherals supply #1, external pnp 1.2/1.5/2.775/3.15 200 vgen2 general peripherals supply #2, external pnp 1.2/1.5/1.6/1.8/2.7/2.8/3.0/3.15 350 vgen3 general peripherals supply #3, internal pmos 1.8/2.9 50 general peripherals supply #3, external pnp 1.8/2.9 250 vusb usb transceiver supply 3.3 100 table 43. power tree summary supply purpose (typical application) output voltage (in v) load capability (in ma)
analog integrated circuit device data freescale semiconductor 73 mc13892 functional device operation supplies the buck regulator topology includes an integrated synchronous rect ifier, meaning that the rectif ying diode is implemented on the chip as a low ohmic fet. the placement of an external diode is therefore not r equired, but overall switcher efficiency may benefit from this. the buck regulator s permit a 100% duty cycle operation. during normal operation, several power modes are possible depending on the loading. for medium and full loading, synchronous pwm control is the most ef ficient, while maintaining a constant switching frequency. two pwm modes are available: the first mode sacrifices low load efficiency for a continuous switching operation (pwm-nps). the second mode offers better low load efficiency by allowing the absence of switching cycles at low output loading (pwm-ps). this pulse skipping feature improves efficiency by reducing dynamic switching losses by simply switching less often. in its lowest power mode, the switcher can regulate using hysteresis control known as a pulse frequency modulation (pfm) control scheme. the frequency spectrum in th is case will be a function of input and output voltage, loading, and the external components. due to its spectral variance an d lighter drive capability, pfm mode is generally reserved for non-active radio mode s and deep sleep operation. buck modes of operation are programmable for explicitly defined or load-dependent control (adaptive). refer to the buck regulators section in power control system for details. common control bits available to each buck regulator may be desi gnated with a suffix ?x? within this specification, where x stands for 1, 2, 3, or 4 (i.e., swx = sw1, sw2, sw3, and sw4). the output voltages of the buck regulators are spi configurable, and two output ranges are available, individually programmed with swxhi for sw2, sw3, and sw4 bucks, sw 1 is limited to only one output range. presets are available for both the normal and standby operation. sw1 and sw2 also include pin controlle d dvs operation. when transitioning from one voltage to another, the output voltage slope is controlled in steps of 25 mv per time step (time step as defined for dvs stepping for sw1 and sw2, fixed at 4.0 s for sw3 and sw4). this allows for support of dyna mic voltage scaling (dvs) by using spi driven voltage steps, state machine defined modes, and direct dvsx pin control. when initially activated, switcher outputs will apply controlled st epping to the programmed valu e. the soft start feature limit s the inrush current at startup. a built-in current limiter ensure s that during normal operation, the maximum current through the coil is not exceeded. this current limiter c an be disabled by setting the swilimb bit. point of load feedback is intended for minimizing errors due to board level ir drops. switching frequency the switchers are driven by a high frequency clock. by default, the pll generat es an effective 3.145728 mhz signal based upon the 32.768 khz oscillator signal by multiplying it by 96. to r educe spurious radio channels, the pll can be programmed via pllx[2:0] to different values as shown in table 44 . to reduce overall current drain, the pll is automatically turned off if all swit chers are in a pfm mode or turned off, and if t he pll clock signal is not needed elsewhere in the system. the cl ocking system provides nearly instantaneously, a high frequency clock to the switchers when the switchers are activated or ex it the pfm mode for pwm mode. the pll can be configured for continuous operation by setting the spi bit pllen = 1. table 44. pll multiplication factor pllx[2:0] multiplication factor switching frequency (hz) 000 84 2 752 512 001 87 2 850 816 010 90 2 949 120 011 93 3 047 424 100 (default) 96 3 145 728 101 99 3 244 032 110 102 3 342 336 111 105 3 440 640
analog integrated circuit device data 74 freescale semiconductor mc13892 functional device operation supplies buck regulator core table 45. pll main characteristics parameter condition (70) min typ max units frequency accuracy ? ? 100 ppm bias current pllen = 1 ? 50 80 a 1 buck regulator active ? 100 150 a 2 buck regulators active ? 115 170 a 3 buck regulators active ? 130 190 a 4 buck regulators active ? 145 210 a start up time cold start ? ? 700 ns pfm to pwm ? ? 600 ns notes 70. clock input to pll is 32.768 khz table 46. pll control registers name r/w reset signal reset state description pllen r/w resetb 0 1 = forces pll on 0 = pll automatically enabled pllx[2:0] r/w reset 100 selects pll multiplication factor table 47. buck regulators (sw1, 2, 3, 4) output voltage programmability set point swx[4:0] swx output, swxhi = 0 (volts) swx output (71) , swxhi = 1 (volts) 0 00000 0.600 1.100 1 00001 0.625 1.125 2 00010 0.650 1.150 3 00011 0.675 1.175 4 00100 0.700 1.200 5 00101 0.725 1.225 6 00110 0.750 1.250 7 00111 0.775 1.275 8 01000 0.800 1.300 9 01001 0.825 1.325 10 01010 0.850 1.350 11 01011 0.875 1.375 12 01100 0.900 1.400 13 01101 0.925 1.425 14 01110 0.950 1.450 15 01111 0.975 1.475 16 10000 1.000 1.500 17 10001 1.025 1.525 18 10010 1.050 1.550 19 10011 1.075 1.575 20 10100 1.100 1.600 21 10101 1.125 1.625 22 10110 1.150 1.650 23 10111 1.175 1.675 24 11000 1.200 1.700 25 11001 1.225 1.725 26 11010 1.250 1.750 27 11011 1.275 1.775
analog integrated circuit device data freescale semiconductor 75 mc13892 functional device operation supplies since the startup default values of the buck regulators are dependent on the state of the pums pin, the swxhi bit settings will likewise be determined by the pums pin. the settings are aligned to the likely application ranges for use cases as given in the defaults tables in power control system . the following tables define the swxhi bit stat es after a startup event is completed, but can be reconfigured via the spi if desired, if an alternate range is needed. care should be taken when changing swxhi bit to avoid unintended jumps in the switcher output. the swxhi se tting applies to normal, standby, and dvs set points for the corresponding switcher. note that the following efficiency curves were measured with the mc13892 in a socket. 28 11100 1.300 1.800 29 11101 1.325 1.825 30 11110 1.350 1.850 31 11111 1.375 1.850 71. output range not available for sw1. sw1 output range is 0.600-1.375, therefore sw1hi = 1 does not apply to sw1. the sw1hi bit should always be set to 0. table 48. swxhi states for power up defaults pums1 ground open vcoredig vcore ground open pums2 open open open open ground ground sw1hi 0 0 0 0 0 0 sw2hi 0 0 0 0 1 1 sw3hi 0 0 0 0 1 1 sw4hi 1 1 1 1 1 1 table 47. buck regulators (sw1, 2, 3, 4) output voltage programmability set point swx[4:0] swx output, swxhi = 0 (volts) swx output (71) , swxhi = 1 (volts)
analog integrated circuit device data 76 freescale semiconductor mc13892 functional device operation supplies figure 17. buck regulator pfm efficiency sw1 pf m mo d e efficien cy vo ut = 0,7 25 v 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 il oa d (m a) e ffi c ie n cy ( %) v i n = 2, 80 0 v v i n = 3, 60 0 v v i n = 4, 65 0 v sw2 pf m mo d e efficien cy vo ut = 1.2 50 v 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 il oa d (m a) efficiency (% ) v i n = 2, 80 0 v v i n = 3, 60 0 v v i n = 4, 65 0 v sw4 pf m mo d e efficien cy vo ut = 1.8 00 v 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 il oa d (m a) efficiency (%) v i n = 2, 80 0 v v i n = 3, 60 0 v v i n = 4, 65 0 v
analog integrated circuit device data freescale semiconductor 77 mc13892 functional device operation supplies figure 18. buck regulator pwm (no pulse skipping) efficiency sw1 pwm no pulse skipp ing mode efficien cy vout = 0,725 v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 0 10203040 5060 7080 90100 ilo a d (m a) effic iency (% ) v in = 3 ,00 0 v v in = 3 ,60 0 v v in = 4 ,65 0 v sw4 pwm no pulse skipp ing mode efficien cy vout = 1.800 v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 0 50 1 00 1 50 20 0 2 50 30 0 35 0 400 450 5 00 5 50 60 0 65 0 700 750 8 00 850 9 00 il oa d (m a) effic iency (%) v in = 3,0 00 v v in = 3,6 00 v v in = 4,6 50 v sw2 pwm no pulse skipp ing mode efficien cy vout = 1.250 v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 0 10203040 5060 7080 90100 ilo a d (m a) e f fic ien cy (% ) v in = 3 ,00 0 v v in = 3 ,60 0 v v in = 4 ,65 0 v sw2 pwm no pulse skipp ing mode efficien cy vout = 1.250 v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 0 50 1 00 1 50 20 0 2 50 30 0 35 0 400 450 5 00 5 50 60 0 65 0 700 750 8 00 850 9 00 il oa d (m a) e f fic ien cy (% ) v in = 3,0 00 v v in = 3,6 00 v v in = 4,6 50 v sw4 pwm no pulse skipp ing mode efficien cy vout = 1.800 v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 0 10203040 5060 7080 90100 ilo a d (m a) e f fic ien cy (% ) v in = 3 ,00 0 v v in = 3 ,60 0 v v in = 4 ,65 0 v sw4 pwm no pulse skipp ing mode efficien cy vout = 1.800 v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 0 50 1 00 1 50 20 0 2 50 30 0 35 0 400 450 5 00 5 50 60 0 65 0 700 750 8 00 850 9 00 il oa d (m a) e f fic ien cy (% ) v in = 3,0 00 v v in = 3,6 00 v v in = 4,6 50 v
analog integrated circuit device data 78 freescale semiconductor mc13892 functional device operation supplies figure 19. buck regulator pw m (pulse skippi ng) efficiency dynamic voltage scaling to reduce overall power consumption, proc essor core voltages can be varied dependi ng on the mode or activity level of the processor. sw1 and sw2 allow for three different set points with controlled transitions to avoi d sudden output voltage changes, which could cause logic disruptions on their loads. pres et operating points for sw1 and sw2 can be set up for: ? normal operation: output value selected by spi bits swx[4:0]. voltage transitions in itiated by spi writes to swx[4:0] are governed by the same dvs stepping rate that is programmed for dvsx pin initiated transitions. ? dvs: output can be higher or lower than normal operation fo r tailoring to application requirements. configured by spi bits swxdvs[4:0] and controlled by a dvsx pin transition. ? standby (deep sleep): can be higher or lower than normal operatio n, but is typically selected to be the lowest state retention voltage of a given process. set by spi bits swxstby[4:0] and controlled by a standby event (standby logically anded with standbysec). voltage transitions initiated by standby are governed by the same dvs stepping that is programmed for dvsx pin initiated transitions. the following tables summarize the set point control and dvs time stepping applied to sw1 and sw2. sw1 pwm pu lse skip ping mo de efficiency vo ut = 0,725 v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 0 10203040 5060 7080 90100 ilo a d (m a) e f fic ien cy (% ) v in = 3 ,00 0 v v in = 3 ,60 0 v v in = 4 ,65 0 v sw1 pwm pulse skipping mo de efficiency vo ut = 0,725 v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 0 50 1 00 150 200 25 0 300 35 0 4 00 450 50 0 55 0 6 00 650 70 0 7 50 800 85 0 90 0 9 50 10 0 0 105 0 il oa d (m a) e f fic ien cy (% ) v in = 3,0 00 v v in = 3,6 00 v v in = 4,6 50 v sw2 pwm pu lse skip ping mo de efficiency vo ut = 1.250 v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 0 10203040 5060 7080 90100 ilo a d (m a) e f fic ien cy (% ) v in = 3 ,00 0 v v in = 3 ,60 0 v v in = 4 ,65 0 v sw2 pwm pu lse skip pin g mod e efficiency vou t = 1.250 v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 0 50 1 00 1 50 20 0 25 0 300 350 4 00 4 50 50 0 55 0 600 650 7 00 7 50 80 0 85 0 900 ilo a d (m a) e f fic ien cy (% ) v in = 3, 000 v v in = 3, 600 v v in = 4, 650 v sw4 pwm pu lse skip ping mo de efficiency vo ut = 1.800 v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 0 10203040 5060 7080 90100 ilo a d (m a) e f fic ien cy (% ) v in = 3 ,00 0 v v in = 3 ,60 0 v v in = 4 ,65 0 v sw4 pwm pulse skipping mo de efficiency vo ut = 1.800 v 0% 10 % 20 % 30 % 40 % 50 % 60 % 70 % 80 % 90 % 100 % 0 50 1 00 1 50 20 0 2 50 30 0 35 0 400 450 5 00 5 50 60 0 65 0 700 750 8 00 850 9 00 il oa d (m a) e f fic ien cy (% ) v in = 3,0 00 v v in = 3,6 00 v v in = 4,6 50 v
analog integrated circuit device data freescale semiconductor 79 mc13892 functional device operation supplies since the switchers have a strong sourcing c apability but no active sinking capability, the rising slope is determined by the switcher, but the falling slope can be influ enced by the load. additionally, as the current capability in pfm mode is reduced, controlled dvs transitions in pfm mode coul d be affected. critically timed dvs trans itions are best assured with pwm mode operation. note that there is a special mode of dvs control for switcher increment / decrement (sid) oper ation described later in this chapter. dvs pin controls are not included for sw3 and sw4. however, voltage transitions programmed through the spi will step in increments of 25 mv per 4.0 s, to allow spi controlled voltage stepping with swx[4:0]. additionally, sw3 and sw4 include standby mode set point programmability. figure 20 shows the general behavior for the switchers when init iated with pin controlled dvs, spi programming or standby control. figure 20. sw1 voltage stepping with pin controlled dvs note that the dvsx input pins are reconfigured for switch er increment / decrement (sid) control mode when spi bit siden = 1. refer to the sid descripti on below for further details. switcher increment / decrement a scheme for incrementing or decrementing the operating set po ints of sw1 and sw2 is desirable for improved dynamic process and temperature compensation (dptc) control in support of fine tuning power domains for the processor supply tree. an increment command will increase the set point voltage by a single 25 mv step. a decrement command will decrease the set point by a single 25 mv step. the transition time fo r the step will be the same as pr ogrammed with swxdvsspeed[1:0] for dvs table 49. dvs control logic table for sw1 and sw2 standby (72) dvsx pin set point selected by 0 0 swx[4:0] 0 1 swxdvs[4:0] 1 x swxstby[4:0] notes 72. standby is the logical andi ng of standby and standbysec table 50. dvs speed select ion for sw1 and sw2 swxdvsspeed[1:0] function 00 25 mv step each 2.0 s 01 (default) 25 mv step each 4.0 s 10 25 mv step each 8.0 s 11 25 mv step each 16 s
analog integrated circuit device data 80 freescale semiconductor mc13892 functional device operation supplies stepping. if a switcher runs out of programmable range (in either direction), as constrained by programmable stops, then the increment or decrement command shall be ignored. the switcher increment / decrement (s id) function is enabled with siden = 1. this will reassign the function of the dvs1 and dvs2 pins, from the default toggling between normal and dvs operating modes, to a jog control mode for the switcher which dvsx is assigned. once enabled, the switcher being controlle d will start at the normal mode set point as programmed with swx[4:0] and await any jog commands from the processor. the adjustment scheme e ssentially intercepts the normal mode set point spi bits (i.e., but not dvs or standby programmed set po ints), and makes any necessary adjustments based on jog up or jog down commands. the modified set point bits are then immediat ely passed to the switching regulator, which would then do a dvs step in the appropriate direction. the spi bits co ntaining normal mode programming are not directly altered. when configured for sid mode, a high puls e on the dvsx pin will indicate one of 3 actions to take, with the decoding as a function of how many contiguous spi clock falling edges are seen while the dvsx pin is held high. the sid protocol is illustrated by way of example, assuming siden = 1, and that dvs1 is contro lling sw1. sw1 starts out at its default value of 1.250 v (sw1 = 11010) and is stepped both up and down vi a the dvs1 pin. the spi bits sw1 = 11010 do not change. the set point adjustment takes place in the sid bl ock prior to bit delivery to the switcher's digital control. figure 21. sid control example for increment & decrement sid panic mode is provided for rapid recovery to the progra mmed normal mode output voltage, so the processor can quickly recover to its high performance capability wit h a minimum of communication latency. in figure 22 , panic mode recovery is illustrated as an increment step, initiated by the detection of the second fall ing spi clock edge, followed by a continuation t o the programmed sw1[4:0] level (1.250 v in this example), due to the detection of the third contiguous falling edge of spi clock while dvs1 is held high. table 51. sid control protocol number of spi clk falling edges while dvsx = 1 function 0 no action. switcher stays at its presently programmed configuration 1 jog down. drive buck regulator output down a single dvs step 2 jog up. drive buck regulator output up a single dvs step 3 or more panic mode. dvs step the buck regulator output to the no rmal mode value as programmed in the spi register sw1 output dvs1 spiclk up down 1.250 1.275 1.250 down 1.225 starting value dvs up dvs down dvs down 12 1 1 spiclk shut down when not used
analog integrated circuit device data freescale semiconductor 81 mc13892 functional device operation supplies figure 22. sid control example for panic mode recovery the system will not respond to a new jog command until it ha s completed a dvs step that may be in progress. any missed jog requests will not be stored. for instance, if a switcher is stepping up in voltage with a 25 mv step over a 4.0 s time, response to the dvsx pin for another step will be ig nored until the dvs step period has expired. however, the panic mode step recovery should respond immediately upon detection of the third spiclk ed ge while the corresponding dvsx pin is high, even if the initia l decode of the jog up command is ignored, because it came in before the previous step was completed. while in sid mode, programmable stops ar e used to set limits on how far up and how far down a sid-controlled buck regulator will be allowed to step. the swxsidmin[3:0] and swxsidmax[3:0] bits can be used to ensure that voltage stepping is confined to within the acceptable bounds for a giv en process technology used for the bb ic. to contain all of the swx voltage setting bits in single banks, t he swxsidmin[3:0] word is shortened to 4-bits, but should be decoded by logic to have an implied leading 0 (i.e., msb = 0, but is not included in the programmable word). for instance, sw1sidmin = 1000 (default value) should be decoded as 01000, which corresponds to 0.800 v (assuming sw1hi = 0). likewise, the swxsidmax[3:0] word is shortened to 4-bits, but should be decoded by logic to have an implied leading 1 (msb = 1, but is not included in the progra mmable word). for instance, sw1sidmax = 1010 (default value) should be decoded as 11010, which corresponds to 1.250 v (again, assuming sw1hi = 0). a new spi write for the active switcher output value with swx[4:0] should take immediate effect, and this becomes the new baseline from which succeeding sid steps are referenced. the swxdvs[4:0] value is not considered during sid mode. the system only uses the swx[4:0] bi ts and the min/max stops swxsid min[3:0] and sw xsidmax[3:0]. when in sid mode, a standby = 1 event (pin states of standby and standbysec ) will have the ?immedi ate? effect (after any stbydly delay has timed out) of changing the set point and mode to those defined for standby operation. exiting standby puts the system back to the normal mode set point with no stored sid adjustments -- the system will recalibrate itself again fr om the refreshed baseline. boost regulator swbst is a boost switching regulator with a fixed 5.0 v output. it runs at 2/3 of the sw itcher pll frequency. swbst supplies the vusb regulator for the usb system in otg mode, and it also supplies the power for the rgb led's. when swbst is configured to supply the vbus pin in otg mode, the feedback will be switched to sense the uvbus pin instead of the swbstfb pin. therefore, when driving the vbus for otg mode the output of the switcher may rise to 5.75 v to compensate for the voltage drops on the internal switches. note that the parasitic l eakage path for a boost regulato r will cause the output voltage swbstout and swbstfb to sit at a schott ky drop below the battery voltage whenever swbst is disabled. the switching nmos transistor is integr ated on-chip. an external fly back schottky diode, inductor and capacitor are required. sw1 output dvs1 spiclk up 1.050 starting value dvs up sid panic mode example panic dvs step all the way back to 1.250v (sw1[4:0] programmed value = 1.250v) 3 12 spiclk shut down when not used
analog integrated circuit device data 82 freescale semiconductor mc13892 functional device operation supplies figure 23. boost regulator architecture enabling of swbst is accomplished through the swbsten spi control bit. figure 24. boost regulator efficiency linear regulators this section describes the linear regulators provided. for conveni ence, these regulators are named to indicate their typical or possible applications, but the supplies are not limited to these uses and may be applied to any loads within the specified regu lator capabilities. a low-power standby mode controlled by standby is provided in which the bias current is aggressively reduced. this mode is useful for deep sleep operation where certain supplies cannot be disabled, but active regulation can be tolerated with lesse r parametric requirements. the output driv e capability and performance are limited in this mode. refer to standby event definition and control in power control system for more details. some dedicated regulators are covered in their related chapters rather than in the supplies chapter (i.e., the vusb and vusb2 supplies are included in connectivity ). apart from the integrated linear regulators, there are also gpo output pins provided to enabl e and disable discrete regulators or functional blocks, or to use as a gener al purpose output for any syst em need. for exampl e, one application may be to enable a battery pack thermistor bias in synchronization with timed adc conversions. table 52. switch mode supply swbst control function summary parameter value function swbsten 0 swbst off 1 swbst on 5v boost efficiency (vin = 3.6v, vout = 5v) 80.00 85.00 90.00 95.00 100.00 0100200300 boost load current (ma) ef ficiency (%)
analog integrated circuit device data freescale semiconductor 83 mc13892 functional device operation supplies all regulators use the main bandgap as the reference. the main bandgap is bypassed with a capacitor at refcore. the bandgap and the rest of the core circuitry is supplied from vcor e. the performance of the regula tors is directly dependent on the performance of vcoredig and the bandgap. no external dc loading is allowed on vcoredig or refcore. vcoredig is kept powered as long as there is a valid supply and/or coin cell. table 53 captures the main characteri stics of the core circuitry. regulators general characteristics the following applies to all linear r egulators unless otherwise specified. ? specifications are for an ambi ent temperature of -40 to +85 c. ? advised bypass capacitor is the murata? gr m155r60g225me15 which comes in a 0402 case. ? in general, parametric performance specifications assume the use of low esr x5r ceramic capacitors with 20% accuracy and 15% temperature spread, for a worst case stack up of 35 % from the nominal value. use of other types with wider temperature variation may require a larg er room temperature nominal capacitanc e value to meet performance specs over temperature. in addition, capacitor derating as a function of dc bias voltage requires special attention. finally, minimum bypass capacitor guidelines ar e provided for stability and transient performance. larger values may be applied; performance metrics may be altered and general ly improved, but should be conf irmed in system applications. ? regulators which require a minimum output capacitor esr (thos e with external pnps) can avoid an external resistor if esr is assured with capacitor specificatio ns, or board level trace resistance. ? the output voltage tolerance specified for each of the linear regulators include proc ess variation, temperature range, static line regulation, and static load regulation. ? the psrr of the regulators is measured with the perturbed signal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the perturbed signal. during measurements care must be taken not to reach the drop out of the regulator under test. ? in the low-power mode the output performanc e is degraded. only those parameters listed in the low-power mode section are guaranteed. in this mode, the output current is lim ited to much lower currents than in the active mode. ? regulator performance is degraded in the extended input volt age range. this means that the supply still behaves as a regulator and will try to hold up the output voltage by turning the pass device fully on. as a result, the bias current will in crease and all performance parameters will be heavily degraded, such as psrr and load regulation. ? note that in some cases, the minimum operating range specif ications may be conflicting due to numerous set point and biasing options, as well as the potential to run bp into one of the software or hardware s hutdown thresholds. the specifications are general guidelines which should be interpreted with some care. ? when a regulator gets disabled, the output will be pulled towa rds ground by an internal pull-down. the pull-down is also activated when resetb goes low. ?32 khz spur levels are specified for fully loaded conditions. table 53. core specifications reference parameter target vcoredig (digital core supply) output voltage in on mode (73) , (74) 1.5 v output voltage in off mode (74) 1.2 v bypass capacitor 2.2 f typ (0.65 f derated) vcore (analog core supply) output voltage in on mode (73) , (74) 2.775 v output voltage in off mode (74) 0.0 v bypass capacitor 2.2 f typ (0.65 f derated) refcore (bandgap / regulator reference) output voltage (73) 1.20 v absolute accuracy 0.50% temperature drift 0.25% bypass capacitor 100 nf typ (65 nf derated) notes 73. 3.0 v < bp < 4.65 v, no external loading on vcoredig, vcore, or refc ore. extended operation down to uvdet, but no system malfunction. 74. the core is in on mode when charging or when the state machine of the ic is not in the off mode nor in the power cut mode. o therwise, the core is in off mode.
analog integrated circuit device data 84 freescale semiconductor mc13892 functional device operation supplies ? short-circuit protection (scp) is included on certain ldos (see the scp section later in this chapter). exceeding the scp threshold will disable the regulator and gen erate a system interrupt. the output volt age will not sag below the specified volta ge for the rated current being drawn. for the lower current ldos wit hout scp, they are less access ible to the user environment and essentially self-limiting. ? the power tree of a given application must be scrubbed for crit ical use cases to ensure consistency and robustness in the power strategy. transient response waveforms the transient load and line response are sp ecified with the waveforms as depicted in figure 25 . note that the transient load response refers to the overshoot only, excluding the dc shift itse lf. the transient line response refers to the sum of both ove rshoot and dc shift. this is also valid for the mode transition response. figure 25. transient waveforms short-circuit protection the higher current ldos and those most accessible in product applications include short-circuit detection and protection (vvideo, vaudio, vcam, vsd, vgen1, vgen2, and vgen3). th e short-circuit protection (s cp) system includes debounced fault condition detection, regulator shutdown, and processor inte rrupt generation, to contain failures and minimize chance of
analog integrated circuit device data freescale semiconductor 85 mc13892 functional device operation supplies product damage. if a short-circui t condition is detected, the ldo will be disabled by resetting its vxen bit while at the same time an interrupt scpi will be generated to flag the fault to the system processor. the scpi interrupt is maskable through the scpm mask bit. the scp feature is enabled by setting the regscpen bit. if this bit is not set, then not only is no interrupt generated, but al so the regulators will not autom atically be disabled upon a short-circuit detecti on. however, the built-in current limiter will co ntinue to limit the output current of the regulator. note that by def ault, the regscpen bit is not set, so at startup none of the regu lators that are in an overload condition will be disabled vaudio and vvideo supplies the primary applications of these power supplies are for audi o, and tv-dac. however these supplies could also be used for other peripherals if one of these function s is not required. low-p ower modes and programmable standby options can be used to optimize power efficiency during deep sleep modes. an external pnp is utilized for vvideo to avoid excess on-chip power dissipation at high loads, and large differential between bp and output settings. for stability reasons a small minimu m esr may be required. in the low-power mode for vvideo an internal bypass path is used instead of the external pnp. exter nal pnp devices are always to be connected to the bp line in the application. the recommended pnp device is the on semiconductor nss12100xv6t1g which is capable of handling up to 250 mw of continuous dissipatio n at minimum footprint and 75 c of ambient. for use cases where up to 500mw of dissipation is required, the recommended pnp device is the on semiconductor ? nss12100uw3tcg. for stability reasons a small minimum esr may be required. vaudio is implemented with an integrated pmos pass fet and has a dedicated input supply pin vinaudio. the following tables contain the s pecifications for the vvideo, vaudio. low voltage supplies vdig and vpll are provided for isolated biasing of the baseband system plls for clock generati on in support of protocol and peripheral needs. depending on the lineup an d power requirements, these supplies may be considered for sharing with other loads, but noise injection must be avoided and filtering added if necessary, to ensure suitable pll performance. the vdig and vpll regulators have a dedicated input supp ly pin: vindig for the vdig regulator, and vinpll for the vpll regulator. vindig and vinpll can be connected to either bp or a 1.8v switched mo de power supply rail, such as from sw4 for the two lower set points of each regulator vpll[1:0] and vdig[1:0] = [00], [01]. in addition, when the two upper set points are used vpll[1:0] and vdig[1:0] = [10], [11], the inputs (vindig and vinpll) can be connected to either bp of a 2.2 v nominal external switched mode power supply rail to improve power dissipation. table 54. vvideo and vaudio voltage control parameter value function iload max vvideo 00 output = 2.700 v 250 ma / 350 ma 01 output = 2.775 v 250 ma / 350 ma 10 output = 2.500 v 250 ma / 350 ma 11 output = 2.600 v 250 ma / 350 ma vaudio 00 output = 2.300 v 150 ma 01 output = 2.500 v 150 ma 10 output = 2.775 v 150 ma 11 output = 3.000 v 150 ma table 55. vpll and vdig voltage control parameter value function iload max input supply vpll[1:0] 00 output = 1.2 v 50 ma bp or 1.8 v 01 output = 1.25 v 50 ma bp or 1.8 v 10 output = 1.5 v 50 ma bp or external switcher 11 output = 1.8 v 50 ma bp or external switcher vdig[1:0] 00 output = 1.05 v 50 ma bp or 1.8 v 01 output = 1.25 v 50 ma bp or 1.8 v 10 output = 1.65 v 50 ma bp or external switcher 11 output = 1.8 v 50 ma bp or external switcher
analog integrated circuit device data 86 freescale semiconductor mc13892 functional device operation supplies peripheral interfacing ic interfaces in the lineups generally fall in two categories : low voltage io primarily associ ated with the ap ic and certain peripherals at spivcc level (powered from sw4), and a higher volt age interface level associated with other peripherals not compatible with the 1.8 v spivcc. viohi is provided at a fixed 2.775 v level for such interfaces, and may also be applied to other system needs within the guidelines of the regulator spec ifications. the input viniohi is not only used by the viohi regulator, but also by other bl ocks, therefore it should always be connected to bp, even if the viohi regulator is not used by the system. viohi has an internal pmos pass fet which will support loads up to 100 ma. camera the camera module is supplied by the regulator vcam. this al lows powering the entire module independent of the rest of other parts of the system, as well as to select from a number of vcam output levels for camera vendor flexibilit y. in applicati ons with a dual camera, it is anticipated that only one of the two came ras is active at a time, allowing the vcam supply to be shar ed between them. vcam has an internal pmos pass fet which will support up to 2.0 mpixel camera modules (<65 ma). to support higher resolution cameras, an external pnp is provided. the external pnp configuration is offered to avoid excess on-chip power dissipation at high loads, and large diffe rential between bp and output settings. for lower current requirements, an integrated pmos pass fet is included. the input pin fo r the integrated pmos option is shared wit h the base current drive pin for the pnp option. the external pnp configuration must be committed as a hardwired board level implementat ion, while the operating mode is selected through the vcamconfig bit af ter startup. the vcam is not automatica lly enabled during the power up sequence, allowing software to properly set the vcamconfig bit before t he regulator is activated. the recommended pnp device is the on semiconductor nss12100xv6t1g which is capable of handling up to 250 mw of continuous dissipation at a minimum footprint and 75 c of ambient. for use cases where up to 500 mw of dissipation is required, the recommended pnp device is the on semiconductor nss12100uw3tcg. for stability reasons a small minimum esr may be required. the input vincam should always be connected to bp, even if the vcam regulator is not used by the system. multi-media card supply this supply domain is generally intended for user accessible multi-media cards, such as micro-sd (transflash), rs-mmc, and the like. an external pnp is utilized for this ldo to avoid excess on-chip power dissipation at high loads and large differ ential between bp and output settings. the external pnp device is alwa ys connected to the bp line in the application. vsd may also be applied to other system needs within the guidelines of the regul ator specifications. the recommended pnp device is the on semiconductor nss12100xv6t1g, which is capable of handling up to 250 mw of continuous dissipati on at a minimum footprint and 75 c of ambient. for use cases where up to 500 mw of dissipation is required, the recommended pnp device is the on semiconductor nss12100uw3tcg. for stability reasons a small minimum esr may be required. at the 1.8 v set point, the vsd regulator can be powered from an external buck regulator (2.2 v typ) for an efficiency advantage and reduced power dissipation in the pass devices. table 56. vcam voltage control parameter value output voltage iload max vcamconfig=0 internal pass fet vcamconfig=1 external pnp vcam[1:0] 00 2.5 v 65 ma 250 ma 01 2.6 v 65 ma 250 ma 10 2.75 v 65 ma 250 ma 11 3.00 v 65 ma 250 ma
analog integrated circuit device data freescale semiconductor 87 mc13892 functional device operation supplies gen1, gen2, and gen3 regulators general purpose ldos vgen1, vgen2, and vgen3 are provided for expansion of th e power tree to support peripheral devices, which could include wlan, bt, gps, or other functional modules. all the regulators include programmable set points for system flexibi lity. at the 1.2 v and 1.5 v set points, both vgen1 and vgen2 can be powered from an external buck regulator (2.2 v typ) for an efficiency advantage, and reduced power dissipation in the pass devices. (note th at a connection to bp or the external buck regulator as the input to the regulators is a hardwired board level commitm ent, and not changed on-the-fly). vgen3 has an internal pmos pass fet which will support loads up to 50 ma. for higher current capability, drive for an external pnp is provided. the external pnp configuration is offe red to avoid excess on-chip power dissipation at high loads, an d large differential between bp and output settings. the input pin fo r the integrated pmos option is shared with the base current drive pin for the pnp option. the external pnp configuration must be committed as a hardwired board level implementation, while the operating mode is selected through the vgen3config bit afte r startup. the vgen3 is not aut omatically enabled during the power up sequence, allowing software to properly set the vg en3config bit before the regulator is activated. the recommended pnp device is the on semiconductor nss12100xv6t1g, which is capable of handling up to 250 mw of table 57. vsd voltage control parameter value output voltage iload max input supply vsd[2:0] 000 1.80 v 250 ma bp or external switcher 001 2.00 v 250 ma bp 010 2.60 v 250 ma bp 011 2.70 v 250 ma bp 100 2.80 v 250 ma bp 101 2.90 v 250 ma bp 110 3.00 v 250 ma bp 111 3.15 v 250 ma bp table 58. vgen1 control register bit assignments parameter value function iload max (75) input supply vgen1[1:0] 00 output = 1.20 v 200 ma bp or external switcher 01 output = 1.50 v 200 ma bp or external switcher 10 output = 2.775 v 200 ma bp 11 output = 3.15 v 200 ma bp notes 75. the max load given for vgen1mode = 0 and must take into account the capabilities of the external pass device and operating conditions, to manage its power dissipation. load capability is 3.0 ma for vgen1mode = 1. table 59. vgen2 control register bit assignments parameter value function iload max (76) input supply vgen2[2:0] 000 output = 1.20 v 350 ma bp or external switcher 001 output = 1.50 v 350 ma bp or external switcher 010 output = 1.60 v 350 ma bp 011 output = 1.80 v 350 ma bp 100 output = 2.70 v 350 ma bp 101 output = 2.80 v 350 ma bp 110 output = 3.00 v 350 ma bp 111 output = 3.15 v 350 ma bp notes 76. the max load is given for as vgen2mode = 0, and must take into account the capabiliti es of the external pass device and operating conditions to manage its power diss ipation. load capability is 3.0 ma for vgen2mode = 1.
analog integrated circuit device data 88 freescale semiconductor mc13892 functional device operation supplies continuous dissipation at minimum footprint and 75 c of ambient. for use cases where up to 500 mw of dissipation is required, the recommended pnp device is the on semiconductor nss12100uw3tcg. for stability reasons a small minimum esr may be required. a short circuit condition will shut down the vgen 3 regulator and generate an interrupt for scpi. table 60. vgen3 voltage control vgen3 bit output voltage iload max vgen3config = 0 internal pass fet vgen3config = 1 external pnp 0 1.80 v 50 ma 200 ma 1 2.90 v 50 ma 200 ma
analog integrated circuit device data freescale semiconductor 89 mc13892 functional device operation battery interface and control battery interface and control the battery management interfac e is optimized for applications with a single charger connector to which a standard wall charger or a usb host can be connected. it can also support dead battery operatio n and unregulated chargers. charge path charger line up the charge path is depicted in the following diagram. figure 26. charge path block diagram transistors m1 and m2 control the charge current and provide vo ltage regulation. the latter is used as the top off change voltage, and as the regulated supply voltage to the application in case of a dead battery opera tion. in order to support dead battery operation, a so called ?serial path? charging configuration including m3 needs to be used. then in case of a dead batte ry, the transistor m3 is made non-conducting and the internal trickl e charge current charges the batt ery. if the battery is suffici ently charged, the transistor m3 is made conduct ing which connects the batt ery to the application just like during normal operation without a charger. in so called single path charging, m3 is replaced by a short and the pin battfet must be floating. dead battery operation is not supported in this case. transistors m1 and m2 become non-conducting if the charger voltage is too high . the vbus must be shorted to chrgraw in cases where the wa ll charger and vbus voltages are contained on a common pin. a current can be supplied from the battery to an accessory with all transistors m1, m2, and m3 conducting, by enabling the reverse supply mode. an unregulated wall charger configuration can be built, in wh ich case chrgse1b must be pulled low. the battery current monitoring resistor r1 and the charge led indica tor are optional. more detail on the battery current monitoring can be found in adc subsystem . the preferred devices for m1 and m2 are fairchild? fdz193p, d ue to their small package outline and thermal characteristics. the preferred device for m3 is the on semiconductor nths2101p for its low r dson and small footprint. charger signals the charger uses a number of thresholds for proper operation and will also signal various events to the processor through interrupts. table 61 summarizes the main signals given, including the control bits. for details see the related sections in this chapter and the spi bit summary in spi bitmap . table 61. main control bit signals name description control bits vchrg[2:0] charger regulator voltage setting ichrg[3:0] charger regulator current setting tren internal trickle charger enabling
analog integrated circuit device data 90 freescale semiconductor mc13892 functional device operation battery interface and control thchkb battery thermistor check disable fetovrd, fetctrl spi control over battfet pin (m3) fetovrd: 0 = battfet output are controlled by hardware 1 = battfet controlled by the state of the fetctrl bit fetoctrl: 0 = battfet is driven high if fetovrd is set 1 = battfet is driven low if fetovrd is set rvrsmode reverse mode enabling 0 = reverse mode disabled 1 = reverse mode enabled plim[1:0], plimdis power limiter setting and disabling plimdis: 0 = power limiter enabled 1 = power limiter disabled chrgleden charge led indicator enabling 0 = chrgled disabled 1 = chrgled enabled chgrestart charger state machine restart chgautob selects between standalone or software controlled charging operation 0 = standalone charging 1 = software controlled charging chgautovib allows for spi control over-voltage and current settings in standalone charging mode cyclb controls charging resume behavior 0 = enables cycling 1 = disables cycling interrupt and status bits chgdeti charger attach chgfaulti chrgraw over-voltage, excessive power dissipati on, timeout, battery out of temperature range chgfaults[1:0] charger fault mode sense bits chgens charger enable sense bit usbovi usb over-voltage chgshorti short-circuit detection in reverse mode chgrevi charger path reverse current, detection based on chgcurr threshold chgcurri charge current threshold, detection based on chgcurr threshold cccvi charger path regulation mode, detection based on battcycl threshold chrgse1bi wall charger detect chrgse1bs chrse1b pin sense chrgsss charger configuration sense, serial versus single. a logic 1 indicates a serial path. thresholds chgcurr chrgisns-bpsns at 35 ma flowing into phone, used for end of charge detection, charger removal and charge current reversal battmin batt at 3.0 v, used to increase charge current (40/80 ma and 80/560 ma), detect a dead battery insertion while charging bpon bp at 3.2 v, used to allow turn on when charging fr om usb, closes m3 when in serial path batton batt at 3.4 v, used to allow turn on when charging fr om usb, closes m3 when in serial path battcycl bpsns at 98% of charger voltage setting, us ed to restart charging, used by cccvi table 61. main control bit signals name description
analog integrated circuit device data freescale semiconductor 91 mc13892 functional device operation battery interface and control building blocks and functions the battery management interface consists of several building blocks and functi ons as depicted in the block diagram shown in the previous paragraph. these building blocks and function s are described below while the char ger operation is described in the next section. charge path regulator the m1 and m2 are permanently used as a combined pass devi ce for a super regulator, wit h a programmable output voltage and programmable current limit. the voltage loop consists of m1, m2, and an amplifier with vo ltage feedback taken from the bpsns pin. the value of the sense resistor is of no influence on the output voltage. the out put voltage is programmable by spi through vchrg[2:0] bits. the current loop is composed of the m1 and m2 as control elem ents, the external sense resist or, a programmable current limit, and an amplifier. the control loop will regu late the voltage drop over the external re sistor. the value of the external resisto r therefore is of influence on the charge current. the charge curr ent is programmable by spi through ichrg[3:0] bits. each settin g corresponds to a common use case. software controlled pul sed charging can be obtained by programming the current periodically to zero. table 62. charge path regu lator voltage settings vchrg[2:0] charge regulator output voltage (v) 000 3.800 001 4.100 010 4.150 011 (default) 4.200 100 4.250 101 4.300 110 4.375 111 4.450 table 63. charge path regula tor current limit settings ichrg[3:0] charge regulator current limit (ma) specific use case 0000 0.0 off 0001 80 standalone charging default for pre- charging, usb charging, and lpb 0010 240 0011 320 0100 400 advised setting for usb charging with phy active 0101 480 0110 560 standalone charging default 0111 640 1000 720 1001 800 1010 880 1011 960 1100 1040 1101 1200 high current charger 1110 1600 high current charger 1111 fully on ? m3 open externally powered
analog integrated circuit device data 92 freescale semiconductor mc13892 functional device operation battery interface and control over-voltage protection in order to protect the application, the voltage at the chrgraw pin is monitored. when crossing the threshold, the charge path regulator will be turned off immediatel y, by opening m1 and m2, while m3 gets closed. when the over-voltage condition disappears for longer than the debounce time, charging will resume and previously programmed spi settings will be reloaded. an interrupt chgfaulti is generated with associated chgfaultm mask bit wit h the chgfaults[1:0] bits set to 01. in order to ensure immediate protection, the control of m1, m2, and m3 occurs real-time, so asynchronously to the charger state machine. as a result, for over-voltage conditions of up to 30 s, the charger state machine may not always end up in the over-voltage fault state, and therefore an interrupt may not always be generated. the vbus pin is also protected against over-voltages. this will occur at much lower levels for chrgraw. when a vbus over-voltage is detected the internal circuitry of the usb block is disconnected. a usbovi is ge nerated in this case. for more details see connectivity . when the maximum voltage of the ic is exceeded, damage will occur to the ic and the state of m1 and m2 cannot be guaranteed. if the user wants to protect against these failure conditions, additional protection will be required. table 64. charge path regulator characteristics parameter condition min typ max units input operating voltage chrgraw battmin ? 5.6 v output voltage trimming accuracy vchrg[2:0] = 011 charge current 50 ma at t = 25 c ? ? 0.35 % output voltage spread vchrg[2 :0] = 011, 1xx charge current 1.0 to 100 ma -1.5 ? 1.5 % charge current > 100 ma and above -3.0 ? 1.5 % current limit tolerance (77) ichrg[3:0] =0 001 68 80 92 ma ichrg[3:0] = 0100 360 400 440 ma ichrg[3:0] = 0110 500 560 620 ma all other settings ? ? 15 % start-up overshoot unloaded ? ? 2.0 % configuration input capacitance chrgraw (78) ? 2.2 ? f load capacitor bpsns (78) 10 ? 4.7 f cable length (79) - ? 3.0 m notes 77. excludes spread and tolerances due to board routing and 100 mohm sense resistor tolerances. 78. an additional derating of 35% is allowed. 79. this condition applies when using an external charger with a 3.0 m long cable. table 65. charger over-voltage protection characteristics parameter condition min typ max units over-voltage comparator high voltage threshold high to low, low to high 16 ? 20 v over-voltage comparator debounce time high to low ? 10 ? ms
analog integrated circuit device data freescale semiconductor 93 mc13892 functional device operation battery interface and control power dissipation since the charge path operates in a linear fashion, the dissipation can be significant and care must be taken to ensure that the external pass fets m1 a nd m2 are not over dissipating wh en charging. by default, the ch arge system will protect against this by a built-in power limitation circuit. this circuit will monitor the voltage drop between chrgraw and chrgisns, and the current through the external sense resi stor connected between chrgis ns and bpsns. when required ,.a duty cycle is applied to the m1 and m2 drivers and thus the char ge current, in order to stay within the power budget. at the same time m3 is forced t o conduct to keep the application powered. in case of excessiv e supply conditions, the power limiter minimum duty cycle may not be sufficiently small to maintain the actual power dissipation within budget. in that case, the charge path will be disabled an d the chgfaulti interrupt gene rated with the chgfaults[1:0] bits set to 01. the power budget can be programmed by spi through the plim[1 :0] bits. the power dissipation limiter can be disabled by setting the plimdis bit. in this case, it is advised to use cl ose software control to estimate the dissipated power in the exte rnal pass fets. the power limiter is automatically disabled in serial path factory mode and in reverse mode. since a charger attachment can be a turn-on event when a produc t is initially in the off state, any non-default settings that are intended for plim[1:0] and plimdis, should be programmed ea rly in the configuration sequence, to ensure proper supply conditions adapted to the application. to av oid any false detection during power up, th e power limiter output is blanked at the start of the charge cycle. as a safety precaution though, the power dissipation is monitored and the desired duty cycle is estimated. when this estimated duty cycle fa lls below the power limiter minimum duty cycle, the charger circuit will be disable d. reverse supply mode the battery voltage can be applied to an external accessory via the charge path, by setting the rvrsmode bit high. the current through the accessory supply path is monitored via the c harge path sense resistor r2, and can be read out via the adc. the accessory supply path is disabled and an interrupt chgshorti is generated when the slow or fast threshold is crossed. the reverse path is disabled when a current revers al occurs and an interrupt chrevi is generated. internal trickle charge current source an internal current source between bp and battisns provides small currents to the battery in cases of trickle charging a dead battery. as can be seen under the description of the standal one charging, this source is activated by the charger state machine, and its current level is selected based on the battery voltage. the source can also be enabled in software controlled charging mode by setting the tren bit. this source cannot be used in single path configurat ions because in that case, battisns and bp are shorted on the board. table 66. charger power dissipation limiter control plim[1:0] power limit (mw) 00 (default) 600 01 800 10 1000 11 1200 table 67. charger power dissipation limiter characteristics parameter condition min typ max units power limiter accuracy up to 2x the power set by plim[1:0] ? ? 15 % power limiter control period ? 500 ? ms power limiter blanking period upon charging enabling ? 1500 ? ms power limiter minimum duty cycle ? 10 ? % table 68. accessory supply main characteristics parameter condition min typ max units short-circuit current slow threshold 500 ? ? ma slow threshold debounce time ? 1.0 ? ms short-circuit current fast threshold ? ? 1840 ma fast threshold debounce time ? 100 ? s current reversal threshold current from accessory ? chgcurr ? ma
analog integrated circuit device data 94 freescale semiconductor mc13892 functional device operation battery interface and control charger detection and comparators the charger detection is based on three co mparators. the ?charger valid? monitors chrgraw, the ?char ger presence? that monitors the voltage drop between chrgra w and bpsns, and the ?chgcurr? comparator that monitors the current through the sense resistor conn ected between chrgisns and bpsns. a charger insertion is detected based on the charger presence comparator and the ?charger valid? comparator both going high. for all but the lowest current setting, a charger removal is detected based on both the ?charger pres ence? comparator going low and the c harger current falling below chgcurr. in addition, for the lowest current settings or if not charging, the ?charger valid? comp arator going low is an additional cause f or charger removal detection. the table below summarizes the charger detection logic. in addition to the aforementioned comparat ors, three more comparators play a role in battery charging. these comparators are ?battmin?, which monitors batt for the safe charging bat tery voltage, ?batton?, which monitors batt for the safe operating battery vo ltage, and ?battcycl?, which monitors bpsns for the constant current to constant voltage transition. the battmin and batton comparators have a normal and a long (slow) debounced output. the slow output is used in some places in the charger flow to provide enough time to the batt ery protection circuit to reconnect the battery cell. table 69. internal trickle charger control batt trickle charge current (ma) 0 < batt < battmin 40 battmin < batt < batton 80 table 70. internal trickle charger characteristics parameter condition min typ max units trickle charge current accuracy ? ? 30 % operating voltage battisns 0.0 ? ? v bp-battisns 1.0 ? ? v extended operating range (80) bp-battisns 0.3 ? ? v notes 80. the effective trickle current may be significantly reduced table 71. charger detection setting ichrg[3:0] charger valid comparator charger presence comparator chgcurr comparator charger detected 0000, 0001 0 x x no 1 0 x no 1 1 x yes other settings x 0 0 no x 1 x yes x x 1 yes table 72. charger detectors main characteristics parameter condition min typ max units battmin threshold at batt 2.9 ? 3.1 volts batton threshold at batt 3.3 ? 3.5 volts battcycl threshold at bpsns relative to vchrg[2:0] ? 98 ? % charger presence chrgraw-bpsns 10 ? 50 mv charger valid chrgraw ? 3.8 ? v chgcurr threshold chrgisns-bpsns, current from charger 10 ? 50 ma
analog integrated circuit device data freescale semiconductor 95 mc13892 functional device operation battery interface and control crossing the thresholds battcycl and chgcurr will generate the interrupts cccvi and chgcurri respectively. these interrupts can be used as a simple way to implement a three- bar battery meter. battery thermistor check circuitry a battery pack may be equipped with a thermistor, which value decreases over temperature (ntc ). the relationship between temperature t (in kelvin) and the thermistor value (r t) is well characterized and can be described as rt = r0*e^(b*(1/t-1/t0), with t0 being room temperature, r0 the the rmistor value at t0 and b being the so ca lled b-factor which indicates the slope of the thermistor over temper ature. in order to read ou t the thermistor value, it is biased fr om gpo1 through a pull-up resistor r pu . see also the adc chapter. the battery the rmistor check circuit compares the fracti on of gpo1 at adin5 with two preset thresholds, which correspond to 0 and 45 c, see table 73 . charging is generally allowed when the thermistor is within the range, see next section for details. charge led indicator since normal led control via the spi bus is not always possible in the charging mode, an 8.0 ma max current sink is provided at the chrgled pin for an led connected to chrgraw. the led will be activated when standalone charging is started, and will remain under control of the state machine also when the application is powered on. at the en d of charge, the led is automatically disabled. through the chrgleden bit, the led can be forced on. in software controlled charging, the led is under full control of this chrgleden bit. debounce period battmin, batton rising edge (normal ? 32 ? ms battmin, batton rising edge (slow) ? 1.0 ? s battmin falling edge (slow) ? 1.0 ? s battmin falling edge (fast) ? 1.0 ? s battcycl dual edge ? 100 ? ms chgcurr ? 1.0 ? ms charger detect dual edge ? 100 ? ms table 73. battery thermistor check main characteristics temperature threshold voltage at adin5 corresponding resistor values corresponding temperature (in c) * rpu rt b=3200 b=3500 b=3900 t low 24/32 * gpo1 10 k 30 k -3.0 0.0 +2.0 t high 10/32 * gpo1 10 k 4.5 k +49 +46 +44 table 74. charge led drivers main characteristics parameter condition min typ max units trickle led current chrgled = 2.5 v ? ? 8.0 ma chrgled = 0.7 v 5.0 ? ? ma notes 81. above conditions represent respecti vely a usb and a collapsed charger case table 75. charge led driver control chrgleden chrgled 0 (default) auto 1 on table 72. charger detectors ma in characteristics (continued) parameter condition min typ max units
analog integrated circuit device data 96 freescale semiconductor mc13892 functional device operation battery interface and control charger operation usb charging the usb vbus line in this case, is used to provide a s upply within the usb voltage limits and with at least 500 ma of current drive capability. when trickle charging from the usb cabl e, it is important not to exceed the 100 ma, in case of a legacy usb bus. the appropriate charge current level ichrg[2:0] = (0001) is 80 ma typical which accounts for t he additional current through the charge led indicator. wall charging no distinction can be made between a usb host or a wall charger. therefore, when attaching a wall charger, the chrgse1b pin must be forced low as a charger attach indicator. t he chrgse1b pin has a built-in weak pull-up to vcore. in the application, this pin is preferably pulled low, with for instance an npn of which the base is pulled high through a resistor to chrgraw. the state of the chrgse1b pin is reflected through the chrg se1bs bit. when chrgse1b changes state a chrgse1bi is generated. no specific deboun ce is applied to the chrgse1b detector. if an application is to support wall chargers and usb on se parate connectors, it is advi sed to separate the vbus and the chrgraw on the pcb. for these applications, charging from usb is no longer possible. for proper operation, a 120 kohm pull-down resistor should be placed at vbus. standalone charging a standalone charge mode of operation is provided to minimize so ftware interaction. it also allows for a completely discharged battery to be revived without processor control. this is especial ly important when charging from a usb host or when in single path configuration (m3 replaced by short, battfet floating). since the default voltag e and current setting of the charge path regulator may not be the optimum choice for a given applicatio n, these values can be reprog rammed through the spi if the chgautovib bit is set. note that the power limiter can be programmed independent of this bit being set. upon connecting a usb host to the application with a dead battery, the trickle cycle is started and the current set to the lowe st charge current level (80 ma). when the battery voltage rises above the batton = 3.4 v threshold, a power up sequence is automatically initiated. the lo west charge current level remains selected until a higher charge current level is set through th e spi after negotiation with the usb host. in case of a power up failure , a second power up will not be initiated to avoid an ambulan ce mode, the charger circuitry will though continue to charge. the usb dead battery operation follow ing the low-power boot scheme is described further in this chapter. upon connecting a charger to an application with a dead battery th e behavior will be different for serial path and single path configurations. in serial path (m3 present), the application will be powered up with the current through m1m2 set to 500 ma minimum. the internal trickle charge current source wil l be enabled, set to its lowest level (40 ma) up to battmin, followed by the highest setting (80 ma). the internal trickle charge curr ent is not programmable, but can be turned off by the spi. in this mode, the voltage and current regulation to bp through the external pa ss devices m1m2 can be reprogrammed through the spi. once the battery is greater than batton, it will be connected to bp and further charged through m1/m2 at the same time as the application. in single path (m3 replaced by a short, battfet floating), the ba ttery (and therefore bp) is below the bpon threshold. this will be detected and the external charge path will be used to precharge the battery, up to battmin at the lowest level (80 ma), and above at the 500 ma minimum level. once exceeding bpon, a turn on ev ent is generated and the voltage and current levels can be reprogrammed. when in the serial path and upon initia lization of the charger circuitry, and it appears bp stays below bpon, the application will not be powered up, and the same chargi ng scheme is followed as for single path. table 76. charger detector characteristics parameter condition min typ max units chrgse1b pull-up to v c o r e ? 100 ? kohm logic low 0.0 ? 0.3 v logic high 1.0 ? vcore v
analog integrated circuit device data freescale semiconductor 97 mc13892 functional device operation battery interface and control the precharge will timeout and stop charging, in case it did not succeed in raising the battery to a high enough level: batton for internal precharge, external precharge in the case of usb, and bpon for the exter nal precharge, in case of a charger. this is a fault condition and is flagged to the processor by the chgfaulti interrupt, and the chgfaults[1:0] bits are set to 10. the charging circuit will stop charging and generate a chgcurri inte rrupt after the battery is fully charged. this is detected by the charge current dropping below the chgcurr limit. the char ger automatically restarts if the battery voltage is below battcycl. software can bypass this cyclic mode of operati on by setting the cyclb bit. setting the bit does not prevent interrupts to be generated. during charging, a charge timer is running. when expiring befo re the chgcurr limit is reached, the charging will be stopped and an interrupt generated. the charge timer can be reset before it expires by setting the self clearing chgtmrrst bit. after expiration, the charger needs to be restart ed. proper charge termination and restart is a relatively slow process. therefore in both of the previous cases, the charging will rapidly resume, in ca se of a sudden battery bounce. this is detected by bp dropping below the batton threshold. out of any state and after a timeout, the charger state machi ne can be restarted by removing and reapplying the charger. a software restart can also be initiated by setting the self clearing chgrestart bit. the state of the charger logic is reflected by means of the chgens bit. this bit is t herefore a 1 in all st ates of the charger state machine, except when in a fault condition or when at t he end of charge. in low-power boot mode, the bit is not set until the acklpb bit is set. this also mean s that the chgens bit is not cleared when the power limiter interacts, or when the battery temperature is out of range. the charge led at chrgled follows the st ate of the chgens bit with t he exception that software can force the led driver on. the detection of a serial path versus a single path is reflected through the chrgsss bit. a logic 1 indicates a serial path. in cases of single path, the pin battfet must be left floating. the charging circuit will stop charging, in case the die temper ature of the ic exceeds the th ermal protection threshold. the state machine will be re-initiated again when the temperature drops below this threshold. software controlled charging the charger can also be operated under software control. by setting chgautob = 1, full control of th e charger settings is assumed by software. the state machine will no longer determine the mode of charging. the only exceptions to this are a charger removal, a charger over-voltage detection and excessive power dissipation in m1/m2. for safety reasons, when a resetb occurs, the software contro lled charging mode is exited for the standalone charging operation mode. in the software controlled charging mode, the internal trickle ch arger settings can be controlled as well as the m3 operation through fetctrl (1 = conducting). the latter is only possible if the fetov rd bit is set. if a sudden drop in bp occurs (bp < bpon) while m3 is open, the charger control logic will imme diately close m3 under the condition that batt > battmin. table 77. charger timer characteristics parameter condition min typ max units charger timer ? 120 ? min precharge timer external precharge 80 ma internal precharge 40/80 ma ? 270 ? min external precharge 400/560 ma ? 60 ? min table 78. charger fault conditions fault condition chgfaults[1:0] chgfaulti cleared or no fault condition 00 not generated over-voltage at chrgraw 01 rising edge excessive dissipation on m1/m2 01 rising edge sudden battery drop below battmin 10 rising edge any charge timeout 10 rising edge out of temperature 11 dual edge
analog integrated circuit device data 98 freescale semiconductor mc13892 functional device operation battery interface and control factory mode in factory mode, power is provided to the application with no battery pres ent. it is not a situation which should occur in the field. the factory mode is differentiated from a usb host by, in additi on to a valid vbus, a uid being pulled high to the vbus level during the attach, see connectivity . in case of a serial path (m3 present), t he application will be powered up with m1m2 fully on. the m3 is opened (non conducting) to a separate bp from batt. howe ver, the internal trickle charge current source is not enabled. all the charger timers as well as the power limiter are disabled. in case of a single path (m3 replaced by a short, battfet floating), the behavior is similar to a normal charging case. the application will power up and the charge current is set to the 500 ma minimum level. all the internal timers and pre-charger timers are enabled, while only the charger timer and power limiter function are disabled. in both cases, by setting the chgautovib bit, the char ge voltage and currents can be programmed. when setting the chgautob bit the factory mode is exited. usb low-power boot usb low-power boot allows the application to boot with a dead battery within the 100 ma usb budget until the processor has negotiated for the full current capability. this mode expedites th e charging of the dead battery and allows the software to bri ng up the lcd display screen with the message ?charging battery?. th is is enabled on the ic by hardwiring the mode pin on the pcb board, as shown in table 79 . below are the steps required for usb low-power booting: 1. first step: detect a potential low-power boo t condition, and qualify if it is enabled. a) vbus present and not in factory mode (either via a wall ch arger or usb host, since the ic has no knowledge of what kind of device is connected) b) bpbpon) c) board level enabling of lpb with mode pin hardwired to vcoredig d) m3 included in charger system (serial path charging, not sing le). if all of these are true , then lpbs=1 and the system will proceed with lpb sequence. if any are false, lpbs = 0. 2. if lpbs = 0, then a normal booting of the system will take place as follows: a) mode = gnd. the int pin should behave normally, i.e. c an go high during watchdog phase based on any unmasked interrupt. if bp>batton, the application will turn on. if bp < batton, the pmic will default to trickle charge mode and a turn on event will occur when the battery is charged above the batton threshold. the processor does not support a low-power boot mode, so it powers up normally. b) mode = vcoredig. when coming from cold start the int is kept low throughout the watchdog phase. the processor detects this and will boot normally. the int behavior is becomes 'normal' when entering on mode, and also when entering watchdog phase from warm start. 3. if lpbs = 1, then the system will boot in low- power as follows: a) cold start is initiated in a ?current starved bring- up? limited by the charger system's dac step ichrg[3:0] = 0001 to stay within 100 ma usb budget. the startup sequence and defaults as defined in the startup table will be followed. since vbus is present the usb supplies will be enabled. the charge led driver is maintained off. b) after the power up sequence, but befor e entering watchdog phase, thus rel easing the reset lines, the charger dac current is stepped up to ichrg[3:0] = 0100. this is in advance of negotiation and the application has to ensure that the total loading stays below the un-negotiated 100 ma limit. c) the int pin is made high before ent ering watchdog phase and releasing resetbm cu. all other interrupts are held off during the watchdog phase. the processor detects this and starts up in a low-power mode at low clock speed. d) the application processor will enable the phy in serial fs mode for enumeration. e) if the enumeration fails to get the stepped up current, t he processor will bring wdi low. the power tree is shut down, and the charging system will revert to trickle recovery, lpbs rese t to 0. (or any subsequent failure: wdi = 0). also if resetb transitions to 0 while in lpb (i.e., if bp loading misbehaves and causes a uvdet for example), the system will transition to usb trickle recover, lpbs reset to 0. table 79. mode pin programming mode pin state mode ground normal operation vcoredig low-power boot allowed
analog integrated circuit device data freescale semiconductor 99 mc13892 functional device operation battery interface and control f) if the enumeration is successful to get the stepped up curre nt the processor will hold wdi high and continues with the booting procedure. ? when the spi is activated, the lpb interrupt lpbi can be cleared; other unmasked interrupts may now become active. when leaving watchdog phase for the on mode, the interrupts will work 'normally' even if lpbi is not cleared. ? the spi bit acklpb bit is set to enable the internal trickle charger. the charge led gets activated. when the battery crosses the battmin threshold the m3.transistor is automatical ly closed and the battery is charged with the current not taken by the application. ? when bp exceeds bpon, the charger state machine will succe ssfully exit the trickle c harge mode. this will make lpbs = 0 which generates a lpbi. this interrupt will inform the processor that a full turn on is allowed. once this happens the application code is allowed to run full speed. battery thermistor check operation by default, the battery thermistor value is taken into accoun t for charging the battery. upon detection of a supply at chrgraw, the core circuitry powers up including vcore. as s oon as vcore is ready, the outpu t gpo1 is made active high, independently of the state of gpo1en bit. the resulting voltage at adin5 is compared to the corresponding temperature thresholds. if the voltage at adin5 is wit hin range, the charging will behave as descr ibed thus far, however if out of range th e charger state machine will go to a wait st ate, pause the charge timers, and no current will be sourced to the battery. when the temperature comes back in range, charging is continued again. the actual behavior depends on the configuration the charger circuitry at the moment the temperature range is exceeded. the battery thermistor check ca n be disabled by setting the thchkb bit. this is useful in applications w here battery packs without thermistor may be used. this bit defaults to '0', which means that initial power up on ly can be achieved with an alread y charged battery pack or on a charger, but not on a usb host without low-power boot s upport. alternatively, one can bias adin5 to get within the temperature window. sett ing the spi bit to disable the thermistor check will also inhibit the automatic enabl ing of the gpo1 output. the gpo1 output stil l remains controllable through gpo1en. as an additional feature, the charger state machine will end up in an out of temperature state when the die temperature is below -20 c, independent of the setting of the thchkb bit. notes : ? when using the battery charger as the only source of power, as in a battery-less application, the following precautions should be observed: ? it is still necessary to connect adin5 to either vcoredig or a midpoint of a divi der from gpio1 to ground since the battery charger will still interpret this voltage as the battery pack thermistor by default. ? very careful budgeting of the total current consumption and voltage standoff from chrgra w to bpsns must be made, since the power limiter is operational by default, and a batt ery less system won't have a sour ce of current if the power dissipation limit is reached. ? if operating from a usb host the unit load limit (100 ma max.) must still be observed. ? if operating from a ?wall charger?, and if there is no battery, there is an period of approximately 85 ms after resetb is released, but before the current limit is set to a nominal 560 ma. if the total current demand is greater than this limit, the voltage may collapse and resetb may pulse a few times (depending in part in the system load and dependence on resetb.) therefore, at the end of this time, resetb may or may not be active. it may be necessary to use one of the other turn on events (such as pwronx) to turn it back on. table 80. battery thermistor check charger states configuration state for temperature state for temperature back in range out of range icin ?on? state ic in ?off? state internal precharging on a charger m1m2 = 560 ma / spi setting, m3 = open, itrickle = 0ma internal precharge initialization internal precharging on usb in usb low-power boot m1m2 = 400 ma m3 = open, itrickle = 0ma low-power boot precharge initialization all other non fault charging modes and configurations m1m2 = 0 ma m3 closed initialization initialization
analog integrated circuit device data 100 freescale semiconductor mc13892 functional device operation adc subsystem adc subsystem converter core the adc core is a 10-bit converter. the adc core and lo gic run on 2/3 of the switcher pll generated frequency, so approximately 2.0 mhz. if an adc conversion is requested while the pl l was not active, it will aut omatically be enabled by the adc. a 32.768 khz equivalent time base is derived from this to th e adc time events. the adc is supplied from vcore. the adc core has an integrated auto calibration circui t which reduces the offset and gain errors. the switcher pll is programmable, see supplies . when the switcher frequency is changed, the frequency applied to the adc converter will change accordingly. although the conversion time is inversely proportional to the pllx[2:0] setting, this will n ot influence the adc performance. the locally derived 32.768 khz will remain constant in order not to influence the different timings depending on this time base. input selector the adc has 8 input channels. table 81 gives an overview of the attr ibutes of the a to d channels. the above table is valid when setting the bit adsel = 0 (default). if setting the bit to a 1, the touch screen interface related inputs are mapped on the adc channels 4 to 7 and channels 0 to 3 become unused. for more details see the touch screen interface section. some of the internal signals are first scaled to adapt the signal range to the input range of t he adc. the charge current and the battery current are indirectly read out by the voltage drop over the resistor in the charge path and battery path respectiv ely. for details on scaling see the dedicated readings section. in case the source impedance is not sufficiently low on the di rectly accessible inputs adin5, adin6, adin7, and the muxed gpo4 path, an on chip buffer can be activated through the buffen bit. if this bit is set, the buffer will be active on these sp ecific inputs during an active conversion. outside of the conversions the buffer is automatically disabled. the buffer will add some offset, but will not impact inl and dnl numbers except for input voltages close to zero. table 81. adc inputs channel ada1[2:0] ada2[2:0] signal read input level scaling scaled version 0 000 battery voltage (batt) 0 ? 4.8 v /2 0 ? 2.4 v 1 001 battery current (batt-battisnscc) -60 mv ? 60 mv (82) x20 -1.2 ? 1.2 v 2 010 application supply (bpsns) 0 ? 4.8 v /2 0 ? 2.4 v 3 011 charger voltage (chrgraw) 0 ? 12 v 0 ? 20 v /5 /10 0 ? 2.4 v 0 ? 2.4 v 4 100 charger current (chrgisns-bpsns) -300 mv ? 300 mv (83) x4 -1.2 ? 1.2 v 5 101 general purpose adin5 (battery pack thermistor) 0 ? 2.4 v x1 0 ? 2.4 v 6 110 general purpose adin6 backup voltage (licell) 0 ? 2.4 v 0 ? 3.6 v x1 x2/3 0 ? 2.4 v 0 ? 2.4 v 7 111 general purpose adin7/adin7b 0 ? 2.4 v x1 0 ? 2.4 v general purpose adin7 0 ? bp /2 0 ? 2.4 v general purpose adin7b 0 ? viohi /2 0 ? 1.4 v die temperature ? ? 1.2 ? 2.4 v uid 0 ? 4.8 v /2 0 ? 2.4 v notes 82. equivalent to -3.0 to +3.0 a of current with a 20 mohm sense resistor 83. equivalent to -3.0 to +3.0 a of current with a 100 mohm sense resistor
analog integrated circuit device data freescale semiconductor 101 mc13892 functional device operation adc subsystem when considerably exceeding the maximum input of the adc at the scaled or unscaled inputs, the reading result will return a full scale. it has to be noted that this full scale does not nece ssarily yield a 1023 dec reading, due to the offsets and calib ration applied. the same applies for when going below the minimum input where the corresponding 0000 dec reading may not be returned. control the adc parameters are programmed by the processors via the spi. up to two adc requests can be queued, and locally these requests are arbitrated and executed. when a conversion is finished, an interr upt adcdonei is genera ted. the interrupt can be masked with the adcdonem bit. the adc can start a series of conversions by a rising edge on the adtrig pin or through the spi programming by setting the asc bit. the asc bit will self clear once the conversions are co mpleted. a rising edge on the adtrig pin will automatically mak e the asc bit high during the conversions. when started, always eight conversions will take place; either 1 for each channel (multiple channel mode, rand = 0) or eight times the same channel (single channel mode, bit rand = 1). in single channel mode, the to be converted channel needs to be selected with the ada1[2:0] setting. this setting is not taken into account in multiple channel mode. in order to perform an auto calibration cycle, a series of adc conversion s is started with adccal = 1. the adccal bit is cleared automatically at the end of the co nversions and an adcdonei interrupt is genera ted. the calibration only needs to be performed before a first utilization of the adc after a cold start. the conversion will begin after a small synchronization error of a few microseconds plus a progr ammable delay from 1 (default) to 256 times the 32 khz equivalent time base by programming the bits at o[7:0]. this delay cannot be programmed to 0 times the 32 khz in order to allow the adc core to be initialized during the first 32 khz clock cycle. the ato delay can also be included between each of the conversions by setting the atox bit. once a series of eight a/d conversions is complete, they are stor ed in a set of eight internal registers and the values can be read out by software (except when having do ne an auto calibration cycle). in order to accomplish this, the software must set th e ada1[2:0] and ada2[2:0] address bits to indi cate which values will be read out. this is set up by two sets of addressing bits t o allow any two readings to be read out from t he 8 internal registers. for example, if it is desired to read the conversion value s stored in addresses 2 and 6, the software will need to set ada1[2:0 ] to 010 and ada2[2:0] to 110. a spi read of the a/d result register will return the values of the conversions indexed by ada1[2:0] and ada2[2:0]. add1[9:0] will contain the value indexed by ada1[2:0], and add2[9:0] will contain the conversion value indexed by ada2[2:0]. an additional feature allows for automat ic incrementing of the ada1[2:0] and ada2[2:0] addressing bits. this is enabled with bits adinc1 and adinc2. when these bits are set, the ada1[2:0] and ada2[2:0] addressing bits will automatically increment during subsequent readings of the a/d result register. this allows for rapid reading of the a/d results registers with a minimu m of spi transactions. the adc core can be reset by setting the self clearing adreset bit. as a result the internal data and settings will be reset but the spi programming or readout result s will not. to restart a new adc conversion after a reset, all adc spi control setting s should therefore be reprogrammed. table 82. adc inpu t specification parameter condition min typ max units source impedance no bypass capacitor at input ? ? 5.0 kohm bypass capacitor at input 10 nf ? ? 30 kohm input buffer offset buffen = 1 -5.0 ? 5.0 mv input buffer input range buffen = 1 0.02 ? 2.4 v
analog integrated circuit device data 102 freescale semiconductor mc13892 functional device operation adc subsystem dedicated readings channel 0 battery voltage the battery voltage is read at the batt pin at channel 0. the ba ttery voltage is first scaled as v(batt)/2 in order to fit the input range of the adc. channel 1 battery current the current flowing out of and into the battery can be read via the adc, by monitoring the voltage drop over the sense resistor between batt and battisnscc. this function is enabled by setting batticon = 1. the battery current can be read either in multiple channel mode or in single channel mode. in both cases, the battery terminal voltage at batt, and the voltage difference between batt and bat tisns, are sampled simultaneo usly but conver ted one after the other. this is done to effectively perform the voltage and curr ent reading at the same time. in multiple channel mode, the converted values are read at the assigned channel. in single channel mode and ada1[2:0] = 001, the converted result is available in 4 pairs of battery voltage and current reading as shown in table 84 . if the batticon bit is not set, the adc will return a 0 reading for channel 1. the voltage difference between batt and ba ttisns is first amplified to fit the adc input range as v(batt-battisns)*20. since battery current can flow in both di rections, the conversion is read out in 2' s complement format. positive readings correspond to the current flow out of the battery, and ne gative readings to the current flowing into the battery. table 83. battery voltage reading coding conversion code addn[9:0] voltage at input adc in v voltage at batt in v 1 111 111 111 2.400 4.800 1 000 010 100 1.250 2.500 0 000 000 000 0.000 0.000 table 84. battery current reading sequence adc trigger signals sampled signal converted readout contents 0 batt, batt ? battisnscc batt channel 0 batt 1 ? batt ? battisnscc channel 1 batt ? battisnscc 2 batt, batt ? battisnscc batt channel 2 batt 3 ? batt ? battisnscc channel 3 batt ? battisnscc 4 batt, batt ? battisnscc batt channel 4 batt 5 ? batt ? battisnscc channel 5 batt ? battisnscc 6 batt, batt ? battisnscc batt channel 6 batt 7 ? batt ? battisnscc channel 7 batt ? battisnscc table 85. battery current reading coding conversion code, addn[9:0] voltage at input, adc in mv batt ? battisns in mv current through 20 mohm in ma current flow 0 111 111 111 1200.00 60 3000 from battery 0 000 000 001 2.346 0.117 5.865 from battery 0 000 000 000 0.0 0.0 0.0 ? 1 111 111 111 -2.346 -0.117 5.865 to battery 1 000 000 000 -1200.00 -60 3000 to battery
analog integrated circuit device data freescale semiconductor 103 mc13892 functional device operation adc subsystem the value of the sense resistor used, determines the accuracy of the result as well as the available conversion range. note that excessively high values can impact the operating life of the device due to extr a voltage drop across the sense resistor. channel 2 application supply the application supply voltage is read at the bp pin at channel 2. the battery voltage is first sca led as v(bp)/2 in order to f it the input range of the adc. channel 3 charger voltage the charger voltage is measured at the chrgraw pin at channel 3. the charger vo ltage is first scaled in order to fit the input range of the adc. if the chrgrawdiv bit is set to a 1 (default), then the sca ling factor is a divide by 5, when set to a 0 a di vide by 10. channel 4 charger current the charge current is read by monitoring the voltage drop over the charge current sense resistor. this resistor is connected between chrgisns and bpsns. the voltage difference is first am plified to fit the adc input range as v(chrgisns-bpsns)*4. the conversion is read out in a 2's complement format, see table 89 . the positive reading corresponds to the current flow from charger to battery, the negative reading to the current flowing into the charger terminal. unlik e the battery current and volta ge readings, the charger current readings are not interlea ved with the charger voltage readings, so when rand = 1 a total of 8 readings are executed. the conversion circuit is enabled by se tting the chrgicon bit to a one. if the chrgicon bit is not set, the adc will return a 0 reading for channel 4. the value of the sense resistor used determines not only the accuracy of the result as well as the available conversion range, but also the charge current levels. it is theref ore advised not to select another value than 100 mohm. table 86. battery current reading specification parameter condition min typ max units amplifier gain 19 20 21 amplifier offset -2.0 ? 2.0 mv sense resistor ? 20 ? mohm table 87. application supply voltage reading coding conversion code addn[9:0] voltage at input adc in v voltage at bp in v 1 111 111 111 2.400 4.800 1 000 010 101 1.250 2.500 0 000 000 000 0.000 0.000 table 88. charger voltage reading coding conversion code addn[9:0] voltage at input adc in v voltage at chgraw in v, chrgrawdiv = 0 voltage at chgraw in v, chrgrawdiv = 1 1 101 010 100 2.000 20.000 10.000 0 000 000 000 0.000 0.000 0.000 table 89. charge current reading coding conversion code addn[9:0] voltage at input adc in mv chrgisns ? bpsns in mv current through 100 mohm in ma current flow 0 111 111 111 1200 300.0 3000 to application/battery 0 000 000 001 2.4 0.586 5.865 to application/battery 0 000 000 000 0.0 0.0 0.0 - 1 111 111 111 -2.346 -0.586 5.865 to charger connection 1 000 000 000 -1200 -300.0 3000 to charger connection
analog integrated circuit device data 104 freescale semiconductor mc13892 functional device operation adc subsystem channel 5 adin5 and battery thermistor and battery detect on channel 5, adin5 may be used as a general purpose unscaled input, but in a typical application, adin5 is used to read out the battery pack thermistor. the thermistor will have to be biased with an external pull-up to a voltage rail greater than the adc input range. in order to save current when the thermistor reading is not require d, it can be biased fr om one of the general purpose io's such as gpo1. a resistor divider network should assure the resulting voltage falls within the adc input range in particular when the thermistor check function is used, see battery thermistor check circuitry . when the application is on and supplied by the charger, a battery removal can be detected by a battery thermistor presence check. when the thermistor terminal becomes high-impedance, th e battery is considered being removed. this detection function is available at the adin5 input and can be enabled by setting the battdeten bit. the voltage at adin5 is compared to the output voltage of the gpo1 driver, and wh en the voltage exceeds the battery removal detect threshold, the sense bit battdetbs is made high and after a debounce the battdetbi interrupt is generated. channel 6 adin6 and coin cell voltage on channel 6, adin6 may be used as a general purpose unscaled input. in addition, on channel 6, the voltage of the coin cell connected to the licell pin can be read (licon=1). since the voltage range of the coin cell exceeds the input voltage range of the a dc, the licell voltage is first scaled as v(licell)*2/3. in case the voltage at licell drops below the coin cell disconnect threshold (see clock generation and real time clock ), the voltage at licell can still be read through the adc. channel 7 adin7 and adin7b, uid and die temperature on channel 7, adin7 may be used as a general purpose unscaled input (adin7div = 0) or as a divide by 2 scaled input (adin7div = 1). the latter allows converting signals that are up to twice the adc converter core input range. in a typical application, an ambient light sensor is connected here. a second general purpose input adin7b is available on channel 7. this input is muxed on the gpo4 pin. the input voltage can be scaled by setting the adin7div bit. in the application, a second ambient light sensor is supposed to be connected here. note that the gpo4 will have to be configured to a llow for the proper routing of gpo4 to the adc, see general purpose outputs . in addition, on channel 7, the voltage of the usb id line connected to the uid pin can be read. since the voltage range of the id line exceeds the input voltage range of the ad c, the uid voltage is first scaled as v(uid)/2. also on channel 7, the die temperature can be read out. the re lation between the read out code and temperature is given in table 93 . table 90. battery removal detect specification parameter condition min typ max units battery removal detect threshold (84) ? 31/32 * gpo1 ? v notes 84. this is equivalent to a 10 kohm pull-up and a 10 kohm thermistor at -35 c. table 91. coin cell voltage reading coding conversion code addn[9:0] voltage at adc input (v) voltage at licell (v) 1 111 111 111 2.400 3.6 1 000 000 000 1.200 1.8 0 000 000 000 0.000 0.0 table 92. uid voltage reading coding conversion code addn[9:0] voltage at adc input (v) voltage at uid (v) 1 111 111 111 2.400 4.80 - 5.25 0 000 000 000 0.000 0.0
analog integrated circuit device data freescale semiconductor 105 mc13892 functional device operation adc subsystem adc arbitration the adc converter and its control is based on a single adc c onverter core with the possibility to store two requests, and to store both their results as shown in figure 27 . this allows two independent pieces of software to perform adc requests. figure 27. adc request handling the programming for the two reque sts, the one to the 'adc' and to the 'adc bis', uses the sa me spi registers. the write access to the control of 'adc bis' is handled via the adcbisn bits located at bi t position 23 of the adc control registers, whi ch functions as an extended address bit. by setting this bit to a 1, the control bits which follow are destined for the 'adc bis'. adcbisn will always read back 0 and there is no read access to t he control bits related to 'adc bis'. the read results from the 'adc' and 'adc bis' conversions are available in two separate registers. the following diagram schematically shows how the adc control and result registers are set-up. table 93. die temperature voltage reading parameter minimum typical maximum unit die temperature read out code at 25 c ? 680 ? decimal temperature change per lsb ? +0.4244 c ? c/lsb slope error ? ? 5.0 % table 94. adc channel 7 scaling selection adin7div adin7sel1 adin7sel0 channel 7 routing and scaling 0 0 0 general purpose input adin7, scaling = 1 1 0 0 general purpose input adin7, scaling = 1 / 2 x 0 1 die temperature x 1 0 uid pin voltage, scaling = 1 / 2 0 1 1 general purpose input adin7b, scaling = 1 1 1 1 general purpose input adin7b, scaling = 1 / 2
analog integrated circuit device data 106 freescale semiconductor mc13892 functional device operation adc subsystem figure 28. adc register set for adc bis access there are two interrupts available to inform the processor when the adc has finished its conversions, one for the standard adc conversion adcdonei, and one for the adcbis conv ersion adcbisdonei. these interrupts will go high after the conversion, and can be masked. when two requests are queued, the request fo r which the trigger event occurs the first will be converted the first. during the conversion of the first request, an adtrig trigger event of the other request is igno red, if for the other request the trigmask bit was set to 1. when this bit is set to 0, the other request adtrig trigger event is memorized, and the conversion will take place directly after the conversions of the first request are finished. the following diagram shows th e influence of the trigmask bit. the trigmask bit is particularly of use when an adc conversion has to be lined up to a periodically adtrig initiate d conversion. in case of asc in itiated conversions, the trigmask bit is of no influence. figure 29. trigmask functional diagram to avoid results of previous conversions getting overwritten by a periodical adtrig signal, a single shot function is enabled by setting the adoneshot bit to a one. in that case, only at t he first following conversion, an adtrig trigger event is accepte d. asc events are not affected by this setting. before performing a new single shot conversion, the adoneshot bit first needs to be cleared. note that this bit is available for each of the conv ersion requests 'adc' or 'adc bis', so can be set independently . it is possible to queue two adtrig trig gered conversions. both conversions will be executed with a priority based on the trigmask setting. if both conversion requests have identical trigm ask settings, priority is given to the 'adc' conversion over the 'adc bis' conversion. note that the adoneshot is also taken into account. to avoid that the adtrig input inadvertently triggers a conversion, the adtrigign bit can be set which will ignore any transition on the adtrig pin. the adc completely ignores either adtrig or asc pulses while aden is low. when reading conversion results, it is preferable to make aden = 0. r/ w bi t address bits nul l bi t adc bis0 8 bit address header 24 b it data adc control register 0 r/ w bi t address bits nul l bi t adc bis1 adc control register 1 r/ w bi t address bits nul l bi t adc bis2 adc control register 2 r/ w bi t address bits nul l bi t adc result bits adc result register adc0 r/ w bi t address bits nul l bi t adc bis result bits adc result register adc1 adc control bits adc control bits adc control bits location 43 location 44 location 46 location 45 location 47
analog integrated circuit device data freescale semiconductor 107 mc13892 functional device operation adc subsystem touch screen interface the touch screen interface provides all ci rcuitry required for the readout of a 4-wir e resistive touch screen. the touch screen x plate is connected to tsx1 and tsx2 while the y plate is co nnected to tsy1 and tsy2. a local supply tsref will serve as a reference. several readout possibilities are offered. in order to use the adc inputs and properly convert and readout the values, the bit adsel should be set to a 1. this is valid for touch screen readings as well as for general purpose reading on the same inputs. the touch screen operating modes are configured via th e tsmod[2:0] bits show in the following table. in inactive mode, the inputs tsx1, tsx2, tsy1, and tsy2 ca n be used as general purpose inputs. they are respectively mapped on adc channels 4, 5, 6, and 7. in interrupt mode, a voltage is applied to the x-plate (tsx2) via a weak current source to vcore, while the y-plate is connected to ground (tsy1). when the two plat es make contact both will be at a low po tential. this will generate a pen interrup t to the processor. this detection does not make use of the a dc core or the tsref regulator, so both can remain disabled. in touch screen mode, the xy coordinate pai rs and the contact resistance are read. the x-coordinate is determined by applyin g tsref over the tsx1 and tsx2 pins while performing a high-impedance reading on the y-plate through tsy1. the y coordi nate is determined by applying tsref between tsy1 and tsy2, while reading the tsx1 pin. the contact resistance is measured by appl ying a known current into the tsy1 terminal of the touch screen and through the terminal tsx2, which is grounded. the voltage difference between the two remaining terminals tsy2 and tsx1 is measured by the adc, and equals the voltage across the contact resistance. me asuring the contact resistance helps in determining if the tou ch screen is touched with a finger or stylus. to perform touch screen readings, the pr ocessor will have to select the touch scr een mode, program the delay between the conversions via the ato and atox settings, tr igger the adc via one of the trigger sources, wait for an interrupt indicating the conversion is done, and then read out the dat a. in order to reduce the interrupt rate and to allow for easier noise rejection, the touch screen readings are repeated in the readout sequence. the dummy conversion inserted between the different readings is to allow the references in the system to be pre-biased for the change in touch screen plate polarity and will read out as '0'. table 95. touch screen operating mode tsmod2 tsmod1 tsmod0 mode description x 0 0 inactive inputs tsx1, tsx2, tsy1, tsy2 can be used as general purpose adc inputs 0 0 1 interrupt interrupt detection is active. generates an interrupt tsi when plates make contact. tsi is dual edge sensitive and 30 ms debounced 1 0 1 reserved reserved for a different interrupt mode 0 1 x touch screen adc will control a sequential reading of 2 times a xy coordinate pair and 2 times a contact resistance 1 1 x reserved reserved for a different reading mode table 96. touch screen reading sequence adc conversion signals sampled readout address (85) 0 x position 000 1 x position 001 2 dummy 010 3 y position 011 4 y position 100 5 dummy 101 6 contact resistance 110 7 contact resistance 111 notes 85. address as indicated by ada1[2:0] and ada2[2:0]
analog integrated circuit device data 108 freescale semiconductor mc13892 functional device operation adc subsystem figure 30 shows how the ato and atox settings determine the readout sequence. the ato should be set long enough so that the touch screen can be biased properly before conversions start. figure 30. touch screen reading timing the main resistive touch screen panel characteristics are listed in table 5 . the switch matrix and readout scheme is designed such that the on chip switch resistan ces are of no influence on the overall re adout. the readout scheme however does not account for contact resistances as present in the touch screen connectors. therefore, the touc h screen readings will have to be calibrated by the user or in the factory where one has to point with a stylus the op posite corners of the screen. when reading out the x-coordinate, the 10-bit adc reading repr esents a 10-bit coordi nate with '0' for a coordinate equal to tsx2, and full scale '1023' when equal to tsx1. when reading out the y-coordinate, the 10-bit ad c reading represents a 10-bit coordinate with '0' for a coordinate equal to tsy2, and full scale '1023' when equal to tsy1. when reading the contact resistan ce the 10-bit adc reading represents the voltage drop over t he contact resistance created by th e known current source multiplied by two. the reference for the touch screen is tsref and is powered from vcore. in touch screen operation, tsref is a dedicated regulator. no other loads than the touch screen should be connected here . when the adc performs non touch screen conversions, the adc does not rely on ts ref and the reference can be disabled. in applications not supporting touch screen at all, the tsref can be used as a low current general purpose regulator, or it can be kept disabled and the bypass capacitor omitted. the operating mode of tsref can be controlled with the tsrefen bit in the same way as some other general purpose regulators are controlled, see linear regulators . coulomb counter as indicated earlier on in this section, the current into and from the battery can be read out through the general purpose adc as a voltage drop over the r1 sense resi stor. together with battery voltage reading, the battery capacity can be estimated. a more accurate battery capacity estimation can be ob tained by using the integrated coulomb counter. the coulomb counter (or cc) monitors the current flowing in/out of the battery by integrating the voltage drop across the battery current sense resistor r1, followed by an a to d conversi on. the result of the a to d conversion is used to increase/ decrease the contents of a counter that can be read out by software. this function will require a 10 f output capacitor to perform table 97. touchscreen interface characteristics parameter condition min typ max unit interrupt threshold for pressure application 40 50 60 kohm interrupt threshold for pressure removal 60 80 95 kohm current source inaccuracy over-temperature ? ? 20 % trigge r 1/32k ato+1 ato+1 ato+1 conversions 0, 1, 2 conversions 3, 4, 5 conversions 6, 7 end of conversi on 2 new touchscreen polarization end of conversion 5 new touchscreen polarization touchscreen polarization end of conversion 7 touchscreen de-polarization touchscreen readout for atox=0 trigger 1/32k ato+1 conversion 0 touchscreen polarization touchscreen readout for atox=1 conversion 1 conversion 2 end of conversion 2 new touchscreen pol arization conversion 3 ato+1 ato+1 ato+1 etc.
analog integrated circuit device data freescale semiconductor 109 mc13892 functional device operation adc subsystem a first order filtering of the signal across r1. due to the samp ling of the a to d converter and the filtering applied, the lon ger the software waits before retrieving the information from the cc, th e higher the accuracy. the capacitor will be connected between the pins cfp and cfm, see figure 31 . figure 31. coulomb counter block diagram the cc results are available in the 2's complement ccout[15:0] c ounter. this counter is preferably reflecting 1 coulomb per lsb. as a reminder, 1 coulomb is the equivalent of 1 ampere during 1 second, so a current of 20 ma during 1 hour is equivalent to 72c. however, since the resolution of the a to d converter is much finer than 1c, the internal counts are first to be rescal ed. this can be done by setting the onec[14:0] bits. the ccout[15:0 ] counter is then increased by 1 with every onec[14:0] counts of the a to d converter. for example, onec[14:0] = 000 1010 0011 1101 bin = 2621 dec yields 1c count per lsb of ccout[15:0] with r1 = 20 mohm. the cc can be reset by setting the rstcc bit. this will reset the digital blocks of the cc and will clear the ccout[15:0] counter. the rstcc bit gets automatically cleared at the end of the reset period which may take up to 40 s. the cc is started by setting the startcc bit. the cc is disabled by setting this bit low again. this will not reset the cc settings nor its count ers, so when restarting the cc with startcc, the count will continue. when the cc is running it can be calibrated. an analog and a digital offset calibration is available. the digital portion of th e cc is by default permanently corrected for offset and gain erro rs. this function can be disabled by setting the cccaldb bit. however, this is not advisable. in order to calibrate the analog portion of the cc, the cccala bit is set. this wi ll disconnect the inputs of the cc from the sense resistor and will internally short t hem together. the ccout[15:0] counter will a ccumulate the analog error over time. the calibration period can be freely chosen by the implementer an d depends on the accuracy required. by setting the onec[14:0] = 1 dec this process is sped up significantly. by reading out the cont ents of the ccout[15:0] and taki ng into account the calibrati on period, software can now calculate the error and account for i t. once the calibration period has finished the cccala bit should be cleared again. one optional feature is to apply a dithering to the a to d conv erter to avoid any error in the measurement due to repetitive events. to enable dithering the ccdither bit should be set. in order for this feature to be operational, the digital calibratio n should remain enabled, so the cccaldb bit should not be set. table 98. coulomb counter characteristics parameter condition min typ max unit sense resistor r1 placed in battery path of charger system -? 20 ? m sensed current through r1 1.0 ? 3000 ma on consumption cc active ? 10 20 a resolution 1lsb increment ? 381.47 ? c
analog integrated circuit device data 110 freescale semiconductor mc13892 functional device operation adc subsystem as follows from the previous descrip tion, using the cc requires a number of programming steps. a typical programming example is given below. 1. spi access 1: initialize ? reg 9: write startcc = 1, rstcc = 1, cccala = 1, ccdither = 1, cccaldb = 0 ? rstcc will be self clearing ? register 10 is not to be programmed since by default the onec[14:0] scaler is set to 1 2. wait for analog calibration period 3. spi access 2: set scaler ? reg 10: write onec to desired va lue for cc use, for instance 2621dec 4. spi access 3: read analog offset and reset cc ? reg 9: write startcc = 1, rstcc = 1, cccala = 0, ccdither = 1, cccaldb = 0 ? during the write access, on th e miso read line the most rece nt ccout[15:0] is available ? rstcc will be self clearing from this point on the acc is running properly and ccout[15:0 ] reflects the accumu lated charge. in order to be sure the contents of the ccout[15:0] are valid, a ccfault bit is availa ble. ccfault will be set '1' if t he ccout content is no longer valid, this means the bit gets set when a fault condition occurs and stays latched till cleared by software. there is no interr upt associated to this bit. the follo wing fault conditions are covered. counter roll over: ccout[15:0] = 8000hex this occurs when the contents of ccout[15:0] go from a negative to a positive value or vice versa. software may interpret incorrectly the battery charge by this change in polarity. when ccout[15:0] becomes equal to 8000hex the ccfault is set. the counter stays counting so its contents can still be exploited. battery remova l: 'bp analog integrated circuit device data freescale semiconductor 111 mc13892 functional device operation connectivity connectivity usb interface the mc13892 contains the regulators re quired to supply the phy contained in the i.mx51, i.mx37, i.mx35, and i.mx27 processors. the regulators used to power the external phy in the i.mx51 and i.mx37 are vusb, vusb2, and vusb for the i.mx35 and i.mx27 processors. the mc13892 also provides the 5.0 v supply for usb otg operation. the usb interface may be used for portable product battery charging (refer to battery interface and control for more details on the charging system). finally included are comparators/detectors for vbus and id detection. the usb interface is illustrated in the following diagram . figure 32. usb interface supplies the vusb regulator is used to supply 3.3 v to the external usb phy. the uvbus line of the usb interface is supplied by the host in the case of host mode operation, or by the integrated vbus generation circuit, in the case of usb otg mode operation. the vbus circuit is powered from the swbst boost supply to ensure otg current sourcing compliance through the normal discharge range of the main battery. the vusb regulator can be supplied from the uvbus wire of the cable when supplied by a host in the case of host mode operation, or by the swbst voltage brou ght in at the vinusb pin and internally connected to the vbus pin for otg mode operation. the vusbin spi bit is used to make the se lection between host or otg mode operation as defined in table 99 .
analog integrated circuit device data 112 freescale semiconductor mc13892 functional device operation connectivity the vbusen pin along with th e vusbin spi bit shown in table 99 , control switching swbst to drive vbus in otg mode. when vbusen = 1 and vusbin = 1, swbst will be driving the vbus. in all other cases, the switch from vinusb to uvbus will be open. the vusbin spi bit is initialized by the pums2 pi n configuration at cold start. when the pums2 is open the vusbin spi bit will default to 0, and when pums2 is grounded the vusbin spi bit will default to 1. when pums2 is grounded, the swbst will also be enabled by default by setting the otgswbsten bit = 1. note that (vbusen = 1 and vusbin = 1) only closes the switch between vinusb and uvbus pins, but does not enable swbst (this needs to be enabled by setting the spi bit otgswbsten = 1). in otg mode, vusb and vusb2 will be automatically enabled by setting the spi bit vusbin to a 1. when swbst is supplying the uvbus pin (otg mode), it will generate vbusval id and bvalid interrupts. these interrupts should not be interpreted as being powered by the host by the software, and the vusb supply will continue to be supplied by the swbst output. to prevent the charger from charging in otg mode, the charger should be put into software controlled mode by setting the chgautob = 1, and the charge current set to 0 prior to enabling the swbst to supply the uvbus pin. the vusb regulator defaults to on when pums2 = ground, and is supplied by the swbst output. if a usb host is attached, the switchover to supply the vusb input by the usb cable (uvbu s pin) is a manual switchover, which will require the following steps via software to switch over properly: rece ive bvalid interrupt, disable the vusb regulator (vusben = 0), change the input vusb to uvbus instead of swbst (set vinusb = 0), and then enable the vusb regulator (vusben = 1). it will be up to the processor to determine what type of device is connected, either a usb host or a wa ll charger, and take appropriate action. when the pums2 = open, the vusb regulator will default to off, unless 5.0 v is present on the uvbus pin. if uvbus is detected during cold start then the vusb regulator will be enabled and powered on in the sequence, shown in power control system , and it will default, which is supplied by the uvbus pin. if uvbus is not detected at cold start then the vusb will default to off. if uvbus is detected later, the vusb regulator will be automatically be enabled and supplied from the uvbus pin. the vusb regulator can be enabled independent of otg or ho st mode by setting the vusben spi bit the vusben spi bit is initialized by at startup based on the pums2 configuration. with pums2 open , the vusben will default to a 1 on power up and will reset to a 1, when either resetb is valid or vbu s is invalid. this allows the vusben regulator to be enabled automatically if the vusb regulator wa s disabled by software. with pums2 = gnd the vusben bit will be enabled in the power up sequence shown in power control system . since uvbus is shared with the char ger input at the board level (see battery interface and control ), the uvbus node must be able to withstand the same high voltages as the charger. in over-voltage conditions, the vusb regulator is disabled. the following tables show the usb supplies. vusb2 is implemented with an integrated pmos pass fet and has a dedicated supply pin vinusb2. the pin vinusb2 should always be connected to bp even in cases w here the regulators are not used by the application. table 99. vusb input source control parameter value function vusbin 0 powered by host: uvbus powers vusb 1 otg mode: swbst internally switched to supply t he vusb regulator, and swbst will drive vbus from the vusbin pin as long as vbusen pin is logic high = 1 notes 86. note that (vusbin = 1 and vbusen = 1) only closes the switch between the vinusb and uvbus pins, but does not enable the swbst boost regulator (which should be enabled with otgswbsten = 1). 87. vusbin spi bit initialized by pums2 pin configuration at cold start pums2 = open, vusbin = 0 pums2 = ground, vusbin = 1 table 100. vusb2 voltage control parameter value function iload max vusb2[1:0] 00 output = 2.400 v 50 ma 01 output = 2.600 v 50 ma 10 output = 2.700 v 50 ma 11 output = 2.775 v 50 ma
analog integrated circuit device data freescale semiconductor 113 mc13892 functional device operation connectivity detection comparators vbus detection and qualification is accomp lished with two comparators, detailed in table 101 . comparator results are used to generate associated interrupts, and sense and ma sking bits are available through spi (refer to spi bitmap ). comparator thresholds are specified for the minimum detect levels, and bits can be used in combination to qualify a vbus window. events are communicated via (int pin) interrupts and managed through spi registers to allow the application processor to turn off the phy. as described in battery interface and control , the battery charger system is designed to work with the usb system physical connector. the power input is then brought into an end produc t on the vbus pin of the usb connector. for fault condition robustness, vbus over-voltage protection is included to protect t he system and flag an over-voltage situation to the processor via the usbovi interrupt. id detector the id detector is primarily used to determine if a mini-a or mi ni-b style plug has been inserted into a mini-ab style receptac le on the application. however, it is also su pports two additional modes which are out side of the usb standards: a factory mode and a non-usb accessory mode. the state of the id detection can be read via the spi to poll dedicated sense bits for a floating , grounded, or factory mode condition on the uid pin. there are al so dedicated maskable interrupts for each uid condition as well . the id detector is based on an on-chip pull-up controlled by the idpucntrl bit. if set high the pull-up is a current source, if set low it is a resistor. id100kpu switches in an additional pull-up from vcore to uid (inde pendent of idpucntrl). the uid voltage can be read out via the adc channel adin7, see adc subsystem . the id detector thresholds are listed in table 102 . further interpretations of non-usb accessory detection may be made for custom vendor applications by eval uation of the adin7 conversion reading. table 101. usb detect specifications parameter condition min typ max units v bus valid comparator trip level 4.4 ? 4.65 v v bus valid trip delay including the usbi debounce rising trip delay 20 ? 24 ms falling trip delay 8.0 ? 12 ms bvalid comparator threshold rising and falling edge 4.0 ? 4.4 v bvalid trip delay rising trip delay for turn on event falling trip delay for turn on event 20 8.0 ? ? 40 12 ms over-voltage protection level rising and falling edge 5.6 ? 6.0 v over-voltage protection disconnect time ? ? 1.0 s table 102. id detection thresholds uid pin external connection uid pin voltage idfloats idgnds idfactorys accessory resistor to ground 0.18 * vcore < uid < 0.77 * vcore 0 1 0 non-usb accessory is attached (per cea- 936-a spec) grounded 0 < uid < 0.12 * vcore 0 0 0 a type plug (usb default slave) is attached (per cea-936-a spec) floating 0.89 * vcore < uid < vcore 1 1 0 b type plug (usb host, otg default master or no device) is attached. voltage applied 3.6v < uid (88) 1 1 1 factory mode notes 88. uid maximum voltage is 5.25 v
analog integrated circuit device data 114 freescale semiconductor mc13892 functional device operation lighting system lighting system the lighting system includes backlight drivers for main displa y, auxiliary display, and keypad. the backlight leds are configured in series. three additional drivers ar e provided for rgb or general purpose signaling. backlight drivers the backlight drivers ledmd, ledad and ledkp are independent current sink channels. each driver channel features programmable current levels via ledx[2 :0] as well as programmable pwm duty cycle settings with ledxdc[5:0]. by a combination of level and pwm settings, t he backlight intensity can be adjusted, or a soft start and dimming feature can be implemented. the on period of t he serial led backlight drivers will be adapted to take into account that the serial led switche r startup time is longer than one half the minimum of the period of the backlight drivers. when applying a duty cycle of less than 100% the backlight dr ivers will be turned on and off at a repetition rate high enough to avoid flickering and or beat frequencies with the different types of displays. also , to avoid high frequency spur coupling i n the application, the switching edges of the output drivers are softened. the current level is programmable in a low range mode and in a high range mode through the ledx hi bit. this facilitates the current setting, in case two or more seri al led strings are connected in parallel to the same driver or when using super bright leds. table 103. usb otg specifications parameter condition min typ max units vbus input impedance as a_device 40 - 100 k uid 220k pull-up (89) idpucntrl = 0, resistor to vcore 132 220 308 k uid pull-up (89) idpucntrl = 1, current source from vcore 4.75 5.0 5.25 a uid parallel pull-up (89) id100kpu = 1, resistor to vcore 60 100 140 k notes 89. note that the uid pull-ups are not mut ually exclusive of each other; they are independently controlled by their enable bits and thus multiple pull-ups can be engaged simultaneously. table 104. backlight drivers current programming ledx[2:0] (90) ledx current level (ma) ledxhi = 0 ledxhi = 1 000 0 0 001 3 6 010 6 12 011 9 18 100 12 24 101 15 30 110 18 36 111 21 42 notes 90. ?x represents md, ad and kp
analog integrated circuit device data freescale semiconductor 115 mc13892 functional device operation lighting system ramp up and ramp down patterns are implemented in hardware to re duce the burden of real time software control via the spi to orchestrate dimming and soft start lightin g effects. ramp patterns for each of th e drivers is accessed with the correspondin g ledxramp bit. the ramp itself is gen erated by increasing or decreasing the pwm duty cycle with a 1/32 step every 1/64 seconds. the ramp time is therefore a function of the init ial set pwm cycle and the final pwm cycle. as an example, starting from 0/32 and going to 32/32 will take 500 ms, while going to from 8/32 to 16/32 takes 125 ms. note that the ramp function is executed upon every change in pwm cycle setting when the corresponding ledxramp = 1. if a pwm change is programmed via spi when ledxramp = 0, then the change is immediate rather than spread out over a pwm sweep. a maximum of only two backlight drivers can be activated at the same time, for instance , the main display plus keypad. if all three backlight drivers are enabled throu gh the ledxen bits, meaning none of the duty cycles equals 0/32, then none of the drivers will be activated. if two backlight drivers are enabled, they time-share the external boost regulato r output. the drivers will automatically be enabled and disabled in a 50/50 percent fashion at a sufficien tly high rate. the led drive current will automatically be double d to the same luminosity as in a si ngle backlight driver configuration. figure 33 illustrates the time sharing principle. assume the md domain is represented by 6 series white leds, and the kp domain is represented by 3 ballasted stacks, that include 3 blue leds in each (a diagra m of serial led configurations is includ ed later in this chapter). figure 33. backlight drivers time sharing example the ?one driver active? case shows the general response when driving a single zone of 6 white leds. the ?two drivers active? case shows the ledmd zone driven at twice the current for half the time. table 105. backlight drivers duty cycle programming ledxdc[5:0] (91) duty cycle 000000 0/32, off 000001 1/32 ? ? 010000 16/32 ? ? 011111 31/32 100000 to 111111 32/32, continuously on notes 91. ?x? represents md, ad, or kp external boost ledmd active ledkp active ledmd active one driver active two drivers active ledmd current ledkp current ledmd active ledkp active
analog integrated circuit device data 116 freescale semiconductor mc13892 functional device operation lighting system figure 34 illustrates some possible configurations for the backlight driver. note that when parallel strings are ganged together on a driver channel, ballasting resistance is reco mmended to help balance the currents in each leg. figure 34. serial led configurations in the left most example in figure 34 : ledmd is set at 15 ma (low range), ledkp is set at 30 ma (high range). when both are operated, then the le dmd current will pulse at 30 ma and the ledkp current at 60 ma. this provides an average of 15 ma through the main display backlight leds and 30 ma through the keypad backlights leds. signaling led drivers the signaling led drivers ledr, ledg, ledb are independent current sink channels. each driver channel features programmable current levels via ledx[2 :0] as well as programmable pwm duty cycle settings with ledxdc[5:0]. by a combination of both, the led inte nsity can be adjusted. by driving leds of di fferent colors, color mixing can be achieved. table 106. serial led driver characteristics parameter (92) condition min typ max units output current setting low range mode 0.0 ? 15 ma high range mode 0.0 ? 30 current programming granularity low range mode ? 3.0 ? ma high range mode ? 6.0 ? pwm granularity ? 1/32 ? repetition rate not blinking ? 256 ? hz absolute accuracy ? ? 15 % matching at 400 mv, 21 ma ? ? 3.0 % glow and dimming speed per 1/32 duty cycle step ? 1/64* ? s notes 92. equivalent to 500 ms ramp time when going from 0/32 to 32/32 ledkp ledmd 12 led keypad arrangement 2 led reduced keypad option ledad 6 led main display ledkp ledmd external boost 9 led keypad 6 led main display ledad 6 led main display 3 led aux display ledmd external boost external boost
analog integrated circuit device data freescale semiconductor 117 mc13892 functional device operation lighting system blue leds or bright green leds require more headroom than red and normal green signal leds. in the application, a 5.0 v or equivalent supply rail is therefore requ ired. this is provided by the integrated boost regulator swbst. to make software programming easier, an ledswbsten spi bit has been provided in the blue led register to enable the boost regulator. note the enable for the boost regulator is an or of the following spi bits (swbsten, usbswbsten, and ledswbsten). for more details on the boost regulator and its control, see supplies . as with the backlight driver channels, t he signaling led drivers include ramp up an d ramp down patterns are implemented in hardware. ramp patterns for each of the drivers is accessed with the corresponding ledxramp bit. the ramp itself is gen erated by increasing or decreasing the pwm duty cycle with a 1/32 step every 1/64 seconds. the ramp time is therefore a function of the init ial set pwm cycle and the final pwm cycle. as an example, starting from 0/32 and going to 32/32 will take 500 ms while going to from 8/32 to 16/32 takes 125 ms. note that the ramp function is executed upon every change in pwm cycle setting. if a pwm change is programmed via spi when ledxramp = 0, then the change is immediate rather than spread out over a pwm sweep. for color mixing and in order to guarantee a constant color, the color mixing should be obtained by the current level setting s o that the intensity is set through the pwm duty cycle. in addition, programmable blink rates are provided. blinking is obtained by lowering the pwm re petition rate of each of the drivers through ledxper[1:0], while the on period is determi ned by the duty cycle setting. to avoid high frequency spur couplin g in the application, the switching edges of the output drivers are softened. during b linking, so ledxper[1:0] is not ?00?, rampi ng and dimming patterns cannot be applied. table 107. signaling led drivers current programming ledx[2:0] (93) ledx current level (ma) 000 0.0 001 3.0 010 6.0 011 9.0 100 12 101 15 110 18 111 21 notes 93. ?x? represents for r, g and b table 108. signaling led driv ers duty cycle programming ledxdc[5:0] (94) duty cycle 000000 0/32, off 000001 1/32 ? ? 010000 16/32 ? ? 011111 31/32 1xxxxx 32/32, continuously on notes 94. ?x? represents r, g and b table 109. signal led drivers period control ledxper[1:0] repetition rate units 00 1/256 s 01 1/8 s 10 1 s 11 2 s
analog integrated circuit device data 118 freescale semiconductor mc13892 functional device operation lighting system apart from using the signal led drivers for driving leds they can also be used as ge neral purpose open drain outputs for logic signaling or as generic pwm generator outputs. for the maximum voltage ratings. the enable for the boost regulator is an or of the following spi bits (swbst en, usbswbsten, and ledswbsten). for more details on the boost regulator and its control, see supplies . as with the backlight driver channels, t he signaling led drivers include ramp up an d ramp down patterns are implemented in hardware. ramp patterns for each of the drivers is accessed with the corresponding ledxramp bit. the ramp itself is gen erated by increasing or decreasing the pwm duty cycle with a 1/32 step every 1/64 seconds. the ramp time is therefore a function of the init ial set pwm cycle and the final pwm cycle. as an example, starting from 0/32 and going to 32/32 will take 500 ms while going to from 8/32 to 16/32 takes 125 ms. note that the ramp function is executed upon every change in pwm cycle setting. if a pwm change is programmed via spi when ledxramp = 0, then the change is immediate rather than spread out over a pwm sweep. for color mixing and in order to guarantee a constant color, the color mixing should be obtained by the current level setting s o that the intensity is set through the pwm duty cycle. in addition, programmable blink rates are provided. blinking is obtained by lowering the pwm re petition rate of each of the drivers through ledxper[1:0], while the on period is determi ned by the duty cycle setting. to avoid high frequency spur couplin g in the application, the switching edges of the output drivers are softened. during b linking, so ledxper[1:0] is not ?00?, rampi ng and dimming patterns cannot be applied. table 110. signaling led driver characteristics parameter condition min typ max units absolute accuracy ? ? 15 % matching at 400 mv, 21 ma ? ? 10 % leakage ledxdc[5:0] = 000000 ? ? 1.0 a
analog integrated circuit device data freescale semiconductor 119 mc13892 spi bitmap spi bitmap the complete spi bitmap is given in table 111 with one register per row for a general overview. a color coding is applied which indicates the type of reset for the bits. table 111. spi bitmap mc13892 bitmap color coding: bits reset by resetb bits reset by rtcporb bits reset by offb bits without reset bits reloaded at cold start reserved bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 register register label r/w r/t address 5:0 null data[23:16] data[15:7] data[7:0] 0 interrupt status 0 r/w 0 0 0 0 0 0 0 reserve d reserved chgrgse1bi idgndi idfloati reserved reserved bvalidi reserved lobathi lobatli bponi chgcurri cccvi chgshorti chgrevi chgfaulti chgdeti usbovi idfactoryi vbusv a 1 interrupt mask 0 r/w 0 0 0 0 0 1 0 reserve d reserved chgrgse1bm idgndm idfloatm reserved reserved bvalidm reserved lobathm lobatlm bponm chgcurrm cccvm chgshortm chgrevm chgfaultm chgdetm usbovm idfactorym vbusv a 2 interrupt sense 0 r 0 0 0 0 1 0 0 reserve d reserved reserved idgnds idfloats reserved reserved bvalids reserved lobaths lobatls bpons chgcurrs cccvs chgfaults[1:0] chgens chgdets usbovs idfactorys vbusv a 3 interrupt status 1 r/w 0 0 0 0 1 1 0 spare battdetbi reserved reserved reserved reserved scpi spare clki thwarnhi thwarnli lpbi memhldi warmi pci rtcrsti sysrsti wdiresti pwron2i pwro 4 interrupt mask 1 r/w 0 0 0 1 0 0 0 spare battdetbim reserved reserved reserved reserved scpm spare clkm thwarnhm thwarnlm lpbm memhldm warmm pcm rtcrstm sysrstm wdirestm pwron2m pwro n 5 interrupt sense 1 r 0 0 0 1 0 1 0 spare battdetbs reserved reserved reserved reserved spare clks thwarnhs thwarnls lpbs pwron2s pwro n 6 power up mode sense r 0 0 0 1 1 0 0 spare spare reserved reserved spare spare reserved spare chrgse1b s chrgsss reserved reserved reserved pums2s[1:0] 7 identificatio n r 0 0 0 1 1 1 0 icidcode[5:0] fab[1:0] fin[1:0] icid[2:0] 8 unused r/w 0 0 1 0 0 0 0 9 unused r/w 0 0 1 0 0 1 0 ccout[15:0] ccfault reserved reserved cccala ccca l 10 unused r/w 0 0 1 0 1 0 0 onec[14:0] 11 unused r/w 0 0 1 0 1 1 0 12 unused r/w 0 0 1 1 0 0 0 13 power control 0 r/w 0 0 1 1 0 1 0 coinch en vcoin[2:0] battdete n reserved bpsns[1:0] pcutexpb thsel glbrstenb clk32kmc uen useroffc lk drm usero f 14 power control 1 r/w 0 0 1 1 1 0 0 pcmaxcnt[3:0] pccount[3:0] pct[7:0] 15 power control 2 r/w 0 0 1 1 1 1 0 stbydly[1:0] reserved reserved reserved clkdrv[1:0] reserved reserved spidrv[1:0] wdireset standbyse cinv standbyp riinv pwron3dbnc[1:0] pwron2dbnc[1:0] pwron1bdbnc[1:0] pwron3 r 16 unused r/w 0 1 0 0 0 0 0 17 unused r/w 0 1 0 0 0 1 0 18 memory a r/w 0 1 0 0 1 0 0 mema[23:0] 19 memory b r/w 0 1 0 0 1 1 0 memb[23:0] 20 rtc time r/w 0 1 0 1 0 0 0 rtccalmode[1:0] rtccal[4:0] tod[16:0] 21 rtc alarm r/w 0 1 0 1 0 1 0 rtcdis spare toda[16:0]
analog integrated circuit device data 120 freescale semiconductor mc13892 spi bitmap 22 rtc day r/w 0 1 0 1 1 0 0 day[14:0] 23 rtc day alarm r/w 0 1 0 1 1 1 0 daya[14:0] 24 switchers 0 r/w 0 1 1 0 0 0 0 sw1hi sw1sidmin[3:0] sw1sidmax[3:0] sw1stby[4:0] sw1dvs[4:0] 25 unused r/w 0 1 1 0 0 1 0 sw2hi sw2sidmin[3:0] sw2sidmax[3:0] sw2stby[4:0] sw2dvs[4:0] 26 switchers 2 r/w 0 1 1 0 1 0 0 sw3hi reserved sw3stby[4:0] spare 27 unused r/w 0 1 1 0 1 1 0 sw4hi sw4stby[4:0] spare 28 switchers 4 r/w 0 1 1 1 0 0 0 reserve d swilimb pllx[2:0] pllen sw2dvsspeed[1:0] sw2uom ode sw2mhmi de sw2mode[3:0] reserved siden sw1dvsspeed[1:0] sw1uomo de sw1mhmide 29 switchers 5 r/w 0 1 1 1 0 1 0 swbsten sw4uomod e sw4mhmide sw4mode[3:0] sw3uomo de sw3mhmide 30 regulator setting 0 r/w 0 1 1 1 1 0 0 spare vcam[2:0] vgen3 vusb2[1:0] vpll[1:0] vgen[2:0] vdig[1:0] 31 regulator setting 1 r/w 0 1 1 1 1 1 0 vsd[2:0] vaudio[1:0] 32 regulator mode 0 r/w 1 0 0 0 0 0 0 spare vusb2stby vusb2en spare vpllstby vpllen vgen2m ode vgen2stby vgen2en spare vdigstby vdigen spare viohistby viohi e 33 regulator mode 1 r/w 1 0 0 0 0 1 0 vsdmode vsdstby vsden spare vaudiost by vaudioe n vvideom ode vvideostby vvideoen reserved vcamconfi g vcammod e vcamstby vcamen spare reserved vgen3c o 34 power miscellane ous r/w 1 0 0 0 1 0 0 gpo4adin spare pwgt2spi en pwgt1s pien gpo4stby gpo4en gpo3stby gpo3en gpo2stby gpo2en gpo1stby gpo1en 35 unused r/w 1 0 0 0 1 1 0 36 audio rx 0 r/w 1 0 0 1 0 0 0 37 audio rx 1 r/w 1 0 0 1 0 1 0 38 audio tx r/w 1 0 0 1 1 0 0 39 ssi network r/w 1 0 0 1 1 1 0 40 audio codec r/w 1 0 1 0 0 0 0 41 audio stereo dac r/w 1 0 1 0 0 1 0 42 unused r/w 1 0 1 0 1 0 0 43 adc 0 r/w 1 0 1 0 1 1 0 adcbis 0 spare adinc2 adinc1 chrgra wdiv tsmod[2:0] reserved tsrefen adin7div adreset adin7sel[1:0] buff e 44 adc 1 r/w 1 0 1 1 0 0 0 adcbis 1 adoneshot adtrigign asc atox ato[7:0] ada2[2:0] ada1[2:0] trigmask a ds e 45 adc 2 r 1 0 1 1 0 1 0 add2[9:0] spare spare add1[9:0] 46 adc 3 r/w 1 0 1 1 1 0 0 reserve d icid[2:0] 47 adc 4 r 1 0 1 1 1 1 0 addbis2[9:0] spare spare addbis1[9:0] table 111. spi bitmap mc13892 bitmap color coding: bits reset by resetb bits reset by rtcporb bits reset by offb bits without reset bits reloaded at cold start reserved bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
analog integrated circuit device data freescale semiconductor 121 mc13892 spi bitmap 48 charger 0 r/w 1 1 0 0 0 0 0 chgaut ovib cyclb chgautob chrgrest art chgtmrrs t chrgle den plimdis plim[1:0] rvrsmode spare fetctrl fetovrd thchkb aclpb tren ichrg[3:0] vchrg[2:0] 49 usb 0 r/w 1 1 0 0 0 1 0 reserve d idpucntrl reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved spare reserved reserved reserved reserved reserved reserved 50 charger usb 1 r/w 1 1 0 0 1 0 0 spare spare reserved reserved reserved reserved otgswbs ten reserved id100kpu reserved reserved vusben vusbin 51 led control 0 r/w 1 1 0 0 1 1 0 ledad[2:0] ledaddc[5:0] ledadra mp ledadhi spare ledmd[2:0] ledmddc[5:0] ledmdramp ledmdhi spare 52 led control 1 r/w 1 1 0 1 0 0 0 spare spare spare ledkp[2:0] ledkpdc[5:0] lekpdramp ledkphi spare 53 led control 2 r/w 1 1 0 1 0 1 0 ledg[2:0] ledgdc[5:0] ldedgra mp ledgper[1:0] ledr[2:0] ledrdc[5:0] ldedrramp ledrper[1:0] 54 led control 3 r/w 1 1 0 1 1 0 0 spare spare ledswbste n ledb[2:0] ledbdc[5:0] ldedbramp ledbper[1:0] 55 unused r/w 1 1 0 1 1 1 0 56 unused r/w 1 1 1 0 0 0 0 57 fsl use only r/w 1 1 1 0 0 1 0 58 fsl use only r/w 1 1 1 0 1 0 0 59 fsl use only r/w 1 1 1 0 1 1 0 60 fsl use only r/w 1 1 1 1 0 0 0 61 fsl use only r/w 1 1 1 1 0 1 0 62 fsl use only r/w 1 1 1 1 1 0 0 63 fsl use only r/w 1 1 1 1 1 1 0 table 111. spi bitmap mc13892 bitmap color coding: bits reset by resetb bits reset by rtcporb bits reset by offb bits without reset bits reloaded at cold start reserved bits not available bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
analog integrated circuit device data 122 freescale semiconductor mc13892 spi bitmap the 24 bit wide registers are numbered from 0 to 63, and are re ferenced throughout this document by register number, or represe ntative name as given in the corresponding captions. the contents of all registers are given in the tables defined in this chapter; each table includes the following information: name: name of the bit. spare bits are implemented in the design for future use, but are not assigned. unused bits are not available in the design. reserved bits are not implemented in the design, but are used on other pmics. bit #: the bit location in the register (0-23) r/w: read / write access and control ? r is read access ? w is write access ? r/w is read and write access ? rw1c is read and write access with write 1 to clear ? rwm is read and write access while the device can modify the bit reset: resetting signal ? resetb, which is the same signal as the resetb pin (so bit is held in reset as long as resetb is low) ? rtcporb which is the reset signal of the rtc module (so bit is no longer held in reset once rtc power is good) ? offb which is an internal signal generat ed when transitioning into the off state ? none. there is no reset signal for hardwired bits nor for the bi ts of which the state is determi ned by the power up mode setti ngs default: the value after reset as noted in the default column of the spi map. ? fixed defaults are explicitly declared as 0 or 1. ? * corresponds to read / write bits that are initialized at st artup based on power up mode settings (board level pin connection s) validated at the beginning of cold or warm start. bits are subsequently spi modifiable. ? s corresponds to read only sense bits that continuously monitor an input signal (sense signal is not latched). ? l corresponds to read only sense bits that are latched at startup. ? x indicates that the state does not have an explicitly defined default value which can be specified. for instance, some bits d efault to a value which is dependent on the version of the ic. description: a short description of the bit function, in some cases additional information is included the following tables are intended to give a summarized overview, for details on the bit description, see the individual chapter s. table 112. register 0, interrupt status 0 name bit # r/w reset default description adcdonei 0 rw1c resetb 0 adc has finished requested conversions adcbisdonei 1 rw1c resetb 0 adcbis has finished requested conversions tsi 2 rw1c resetb 0 touch screen wake-up vbusvalidi 3 rw1c offb 0 vbusvalid detect idfactoryi 4 rw1c resetb 0 id factory mode detect usbovi 5 rw1c rtcporb 0 usb over-voltage detection chgdeti 6 rw1c offb 0 charger attach chgfaulti 7 rw1c rtcporb 0 charger fault detection chgrevi 8 rw1c resetb 0 charger path reverse current chgshorti 9 rw1c resetb 0 charger path short circuit cccvi 10 rw1c resetb 0 charger path cc / cv transition detect
analog integrated circuit device data freescale semiconductor 123 mc13892 spi bitmap chgcurri 11 rw1c resetb 0 charge current below threshold warning bponi 12 rw1c offb 0 bp turn on threshold lobatli 13 rw1c resetb 0 low battery low threshold warning lobathi 14 rw1c resetb 0 low battery high threshold warning reserved 15 r 0 for future use bvalidi 16 rw1c offb 0 usb b-session valid interrupt reserved 17 r 0 for future use reserved 18 r 0 for future use idfloati 19 rw1c resetb 0 usb id float detect idgndi 20 rw1c resetb 0 usb id ground detect chrgse1bi 21 rw1c resetb 0 wall charger detect reserved 22 r 0 for future use reserved 23 r 0 for future use table 113. register 1, interrupt mask 0 name bit # r/w reset default description adcdonem 0 r/w resetb 1 adcdonei mask bit adcbisdonem 1 r/w resetb 1 adcbisdonei mask bit tsm 2 r/w resetb 1 tsi mask bit vbusvalidm 3 r/w offb 1 vbusvalidi mask bit idfactorym 4 r/w resetb 1 id factory mask bit usbovm 5 r/w rtcporb 1 usbovi mask bit chgdetm 6 r/w offb 1 chgdeti mask bit chgfaultm 7 r/w rtcporb 1 chgfaulti mask bit chgrevm 8 r/w resetb 1 chgrevi mask bit chgshortm 9 r/w resetb 1 chgshorti mask bit cccvm 10 r/w resetb 1 cccv mask bit chgcurrm 11 r/w resetb 1 chgcurri mask bit bponm 12 r/w offb 1 bponi mask bit lobatlm 13 r/w resetb 1 lobatli mask bit lobathm 14 r/w resetb 1 lobathi mask bit reserved 15 r 1 for future use bvalidm 16 r/w offb 1 bvalidi mask bit reserved 17 r 1 for future use reserved 18 r 1 for future use idfloatm 19 r/w resetb 1 idfloati mask bit idgndm 20 r/w resetb 1 idgndi mask bit chrgse1bm 21 r/w resetb 1 wall charger mask bit table 112. register 0, interrupt status 0 name bit # r/w reset default description
analog integrated circuit device data 124 freescale semiconductor mc13892 spi bitmap reserved 22 r 1 for future use reserved 23 r 1 for future use table 114. register 2, interrupt sense 0 name bit # r/w reset default description unused 0 r 0 not available unused 1 r 0 not available unused 2 r 0 not available vbusvalids 3 r none s vbusvalidi sense bit idfactorys 4 r none s id factory sense bit usbovs 5 r none s usbovi sense bit chgdets 6 r none s chgdeti sense bit chgens 7 r none 0 charger enable sense bit chgfaults0 8 r none s chgrevi sense bit chgfaults1 9 r none s chrgfault sense bit 0 cccvs 10 r none s chrgfault sense bit 1 chgcurrs 11 r none s chgcurri sense bit bpons 12 r none s bponi sense bit lobatls 13 r none s lobatli sense bit lobaths 14 r none s lobathi sense bit reserved 15 r 0 for future use bvalids 16 r none s usb b-session valid sense reserved 17 r 0 for future use reserved 18 r 0 for future use idfloats 19 r none s id float sense bit idgnds 20 r none s id ground sense bit reserved 21 r 0 for future use reserved 22 r 0 for future use reserved 23 r 0 for future use table 115. register 3, interrupt status 1 name bit # r/w reset default description 1hzi 0 rw1c rtcporb 0 1.0 hz time tick todai 1 rw1c rtcporb 0 time of day alarm pwron3i 2 rw1c offb 0 pwron3 event pwron1i 3 rw1c offb 0 pwron1 event table 113. register 1, interrupt mask 0
analog integrated circuit device data freescale semiconductor 125 mc13892 spi bitmap pwron2i 4 rw1c offb 0 pwron2 event wdireseti 5 rw1c rtcporb 0 wdi system reset event sysrsti 6 rw1c rtcporb 0 pwron system reset event rtcrsti 7 rw1c rtcporb 1 rtc reset event pci 8 rw1c offb 0 power cut event warmi 9 rw1c rtcporb 0 warm start event memhldi 10 rw1c rtcporb 0 memory hold event lpbi 11 rw1c rtcporb 0 low-power usb boot detection thwarnli 12 rw1c resetb 0 thermal warning low threshold thwarnhi 13 rw1c resetb 0 thermal warning high threshold clki 14 rw1c resetb 0 clock source change spare 15 rw1c resetb 0 for future use scpi 16 rw1c resetb 0 short-circuit protection trip detection reserved 17 r 0 for future use reserved 18 r 0 for future use reserved 19 r 0 for future use reserved 20 r 0 for future use unused 21 r 0 not available battdetbi 22 rw1c resetb 0 battery removal detect spare 23 rw1c resetb 0 for future use table 116. register 4, interrupt mask 1 name bit # r/w reset default description 1hzm 0 r/w rtcporb 1 1hzi mask bit todam 1 r/w rtcporb 1 todai mask bit pwron3m 2 r/w offb 1 pwron3 mask bit pwron1m 3 r/w offb 1 pwron1 mask bit pwron2m 4 r/w offb 1 pwron2 mask bit wdiresetm 5 r/w rtcporb 1 wdireseti mask bit sysrstm 6 r/w rtcporb 1 sysrsti mask bit rtcrstm 7 r/w rtcporb 1 rtcrsti mask bit pcm 8 r/w offb 1 pci mask bit warmm 9 r/w rtcporb 1 warmi mask bit memhldm 10 r/w rtcporb 1 memhldi mask bit lpbm 11 r/w rtcporb 0 low-power usb detect mask bit thwarnlm 12 r/w resetb 1 thwarnli mask bit thwarnhm 13 r/w resetb 1 thwarnhi mask bit clkm 14 r/w resetb 1 clki mask bit spare 15 r/w resetb 1 for future use scpm 16 r/w resetb 1 short-circuit protection trip mask bit reserved 17 r 1 for future use reserved 18 r 1 for future use reserved 19 r 1 for future use reserved 20 r 1 for future use unused 21 r 1 not available battdetbm 22 r/w resetb 1 battery detect removal mask bit spare 23 r/w resetb 1 for future use table 115. register 3, interrupt status 1
analog integrated circuit device data 126 freescale semiconductor mc13892 spi bitmap table 117. register 5, interrupt sense 1 name bit # r/w reset default description unused 0 r 0 not available unused 1 r 0 not available pwron3s 2 r none s pwron3i sense bit pwron1s 3 r none s pwron1i sense bit pwron2s 4 r none s pwron2i sense bit unused 5 r 0 not available unused 6 r 0 not available unused 7 r 0 not available unused 8 r 0 not available unused 9 r 0 not available unused 10 r 0 not available lpbs 11 r none 0 low-power usb boot sense bit thwarnls 12 r none s thwarnli sense bit thwarnhs 13 r none s thwarnhi sense bit clks 14 r none s clki sense bit spare 15 r none 0 for future use unused 16 r 0 not available reserved 17 r 0 for future use reserved 18 r 0 for future use reserved 19 r 0 for future use reserved 20 r 0 for future use unused 21 r 0 not available battdetbs 22 r none s battery removal detect sense bit spare 23 r none 0 for future use table 118. register 6, power up mode sense name bit # r/w reset default description modes0 0 r none s mode sense decode imodes1 1 r none s pums1s0 2 r none l pums1 state pums1s1 3 r none l pums2s0 4 r none l pums2 state pums2s1 5 r none l reserved 6 r 0 for future use reserved 7 r 0 for future use r eserved 8 r 0 for future use chrgsss (1) 9 r none l charger serial/single mode sense chrgse1bs 10 r none s chrgse1bs sense bit unused 11 r 0 not available spare 12 r none 0 for future use unused 13 r 0 not available reserved 14 r 0 for future use unused 15 r 0 not available unused 16 r 0 not available unused 17 r 0 not available spare 18 r none 0 for future use spare 19 r none 0 for future use reserved 20 r 0 for future use reserved 21 r 0 for future use
analog integrated circuit device data freescale semiconductor 127 mc13892 spi bitmap spare 22 r none 0 for future use spare 23 r none 0 for future use notes 95. chrgsss will latch an updated sens e value when the charger is enabled. table 119. register 7, identification name bit # r/w reset default description rev0 0 r none x revision rev1 1 r none x rev2 2 r none x rev3 3 r none x rev4 4 r none x unused 5 r 0 not available icid0 6 r none 1 generation id icid1 7 r none 1 icid2 8 r none 1 fin0 9 r none x mc13892 fin version fin1 10 r none x fab0 11 r none x mc13892 fab identifier fab1 12 r none x icidcode0 13 r none 0 ic id within generation icidcode1 14 r none 1 icidcode2 15 r none 0 icidcode3 16 r none 0 icidcode4 17 r none 0 icidcode5 18 r none 0 unused 19 r 0 not available unused 20 r 0 not available unused 21 r 0 not available unused 22 r 0 not available unused 23 r 0 not available table 120. register 8, unused name bit # r/w reset default description unused 23-0 r 0 not available table 121. register 9, acc 0 name bit # r/w reset default description startcc 0 r/w rtcporb 0 1 = run, 0=stop rstcc 1 rwc rtcporb 0 1 = reset, self clearing ccdither 2 r/w rtcporb 0 1 = acc dithering enabled, 0= acc dithering disabled cccaldb 3 r/w rtcporb 0 1 = disable digital offset cancellation cccala 4 r/w rtcporb 0 1 = enable analog offset calibration mode reserved 5 r 0 reserved for future use for scaler reserved 6 r 0 reserved for future use (for scaler) ccfault 7 r/w rtcporb 0 1 = ccout contents no longer valid table 118. register 6, power up mode sense name bit # r/w reset default description
analog integrated circuit device data 128 freescale semiconductor mc13892 spi bitmap ccout0 8 r rtcporb 0 coulomb counter ccout1 9 r rtcporb 0 ccout2 10 r rtcporb 0 ccout3 11 r rtcporb 0 ccout4 12 r rtcporb 0 ccout5 13 r rtcporb 0 ccout6 14 r rtcporb 0 ccout7 15 r rtcporb 0 ccout8 16 r rtcporb 0 ccout9 17 r rtcporb 0 ccout10 18 r rtcporb 0 ccout11 19 r rtcporb 0 ccout12 20 r rtcporb 0 ccout13 21 r rtcporb 0 ccout14 22 r rtcporb 0 ccout15 23 r rtcporb 0 table 121. register 9, acc 0
analog integrated circuit device data freescale semiconductor 129 mc13892 spi bitmap table 122. register 10, acc 1 name bit # r/w reset default description onec0 0 r rtcporb 1 accumulated current counter output onec1 1 r rtcporb 0 onec2 2 r rtcporb 0 onec3 3 r rtcporb 0 onec4 4 r rtcporb 0 onec5 5 r rtcporb 0 onec6 6 r rtcporb 0 onec7 7 r rtcporb 0 onec8 8 r rtcporb 0 onec9 9 r rtcporb 0 onec10 10 r rtcporb 0 onec11 11 r rtcporb 0 onec12 12 r rtcporb 0 onec13 13 r rtcporb 0 onec14 14 r rtcporb 0 unused 15 r 0 not available unused 16 r 0 not available unused 17 r 0 not available unused 18 r 0 not available unused 19 r 0 not available unused 20 r 0 not available unused 21 r 0 not available unused 22 r 0 not available unused 23 r 0 not available table 123. register 11, unused name bit # r/w reset default description unused 23-0 r 0 not available table 124. register 12, unused name bit # r/w reset default description unused 23-0 r 0 not available table 125. register 13, power control 0 name bit # r/w reset default description pcen 0 r/w rtcporb 0 power cut enable pccounten 1 r/w rtcporb 0 power cut counter enable warmen 2 r/w rtcporb 0 warm start enable useroffspi 3 r/w resetb 0 spi command for entering user off modes drm 4 r/w rtcporb 0 keeps vsrtc and clk32kmcu on for all states useroffclk 5 r/w rtcporb 0 keeps the clk32kmcu active during user off clk32kmcuen 6 r/w rtcporb 1 enables the clk32kmcu glbrstenb (96) 7 r/w rtcporb 0 global reset function enabled on the pwron3 pin thsel 8 r/w resetb 0 thermal protection threshold select pcutexpb 9 rwm rtcporb 0 pcutexpb=1 at a startup event indicates that pcut timer did not expire (assuming it was set to 1 after booting) unused 10 r 0 not available unused 11 r 0 not available
analog integrated circuit device data 130 freescale semiconductor mc13892 spi bitmap unused 12 r 0 not available unused 13 r 0 not available unused 14 r 0 not available unused 15 r 0 not available bpsns0 16 r/w rtcporb 0 bpsns1 17 r/w rtcporb 0 reserved 18 r 0 for future use battdeten 19 r/w rtcporb 0 enables battery detect function vcoin0 20 r/w rtcporb 0 coin cell charger voltage setting vcoin1 21 r/w rtcporb 0 vcoin2 22 r/w rtcporb 0 coinchen 23 r/w rtcporb 0 coin cell charger enable notes 96. mc13892a/c versions global reset is active low (glbrstenb = 0) mc13892b/d versions global reset is active high (glbrstenb = 1) table 126. register 14, power control 1 name bit # r/w reset default description pct0 0 r/w rtcporb 0 power cut timer pct1 1 r/w rtcporb 0 pct2 2 r/w rtcporb 0 pct3 3 r/w rtcporb 0 pct4 4 r/w rtcporb 0 pct5 5 r/w rtcporb 0 pct6 6 r/w rtcporb 0 pct7 7 r/w rtcporb 0 pccount0 8 r/w rtcporb 0 power cut counter pccount1 9 r/w rtcporb 0 pccount2 10 r/w rtcporb 0 pccount3 11 r/w rtcporb 0 pcmaxcnt0 12 r/w rtcporb 0 maximum allowed number of power cuts pcmaxcnt1 13 r/w rtcporb 0 pcmaxcnt2 14 r/w rtcporb 0 pcmaxcnt3 15 r/w rtcporb 0 unused 16 r 0 not available unused 17 r 0 not available unused 18 r 0 not available unused 19 r 0 not available unused 20 r 0 not available unused 21 r 0 not available unused 22 r 0 not available unused 23 r 0 not available table 127. register 15, power control 2 name bit # r/w reset default description restarten 0 r/w rtcporb 0 enables automatic restart after a system reset pwron1rsten 1 r/w rtcporb 0 enables system reset on pwron1 pin pwron2rsten 2 r/w rtcporb 0 enables system reset on pwron2 pin pwron3rsten 3 r/w rtcporb 0 enables system reset on pwron3 pin table 125. register 13, power control 0 name bit # r/w reset default description
analog integrated circuit device data freescale semiconductor 131 mc13892 spi bitmap pwron1dbnc0 4 r/w rtcporb 0 sets debounce time on pwron1 pin pwron1dbnc1 5 r/w rtcporb 0 pwron2dbnc0 6 r/w rtcporb 0 sets debounce time on pwron2 pin pwron2dbnc1 7 r/w rtcporb 0 pwron3dbnc0 8 r/w rtcporb 0 sets debounce time on pwron3 pin pwron3dbnc1 9 r/w rtcporb 0 standbyinv 10 r/w rtcporb 0 if set then standby is interpreted as active low standbysecinv 11 r/w rtcporb 0 if set then standbysec is interpreted as active low wdireset 12 r/w resetb 0 enables system reset through wdi spidrv0 13 r/w rtcporb 0 spi drive strength spidrv1 14 r/w rtcporb 0 reserved 15 r 0 for future use reserved 16 r 0 clk32kdrv0 17 r/w rtcporb 0 clk32k and clk32kmcu drive st rength (master control bits) clk32kdrv1 18 r/w rtcporb 0 reserved 19 r 0 for future use reserved 20 r 0 reserved 21 r 0 stbydly0 22 r/w resetb 1 standby delay control stbydly1 23 r/w resetb 0 table 128. register 16, unused name bit # r/w reset default description unused 23-0 r 0 not available table 129. register 17, unused name bit # r/w reset default description unused 23-0 r 0 not available table 127. register 15, power control 2 name bit # r/w reset default description
analog integrated circuit device data 132 freescale semiconductor mc13892 spi bitmap table 130. register 18, memory a name bit # r/w reset default description mema0 0 r/w rtcporb 0 backup memory a mema1 1 r/w rtcporb 0 mema2 2 r/w rtcporb 0 mema3 3 r/w rtcporb 0 mema4 4 r/w rtcporb 0 mema5 5 r/w rtcporb 0 mema6 6 r/w rtcporb 0 mema7 7 r/w rtcporb 0 mema8 8 r/w rtcporb 0 mema9 9 r/w rtcporb 0 mema10 10 r/w rtcporb 0 mema11 11 r/w rtcporb 0 mema12 12 r/w rtcporb 0 mema13 13 r/w rtcporb 0 mema14 14 r/w rtcporb 0 mema15 15 r/w rtcporb 0 mema16 16 r/w rtcporb 0 mema17 17 r/w rtcporb 0 mema18 18 r/w rtcporb 0 mema19 19 r/w rtcporb 0 mema20 20 r/w rtcporb 0 mema21 21 r/w rtcporb 0 mema22 22 r/w rtcporb 0 mema23 23 r/w rtcporb 0
analog integrated circuit device data freescale semiconductor 133 mc13892 spi bitmap table 131. register 19, memory b name bit # r/w reset default description memb0 0 r/w rtcporb 0 backup memory b memb1 1 r/w rtcporb 0 memb2 2 r/w rtcporb 0 memb3 3 r/w rtcporb 0 memb4 4 r/w rtcporb 0 memb5 5 r/w rtcporb 0 memb6 6 r/w rtcporb 0 memb7 7 r/w rtcporb 0 memb8 8 r/w rtcporb 0 memb9 9 r/w rtcporb 0 memb10 10 r/w rtcporb 0 memb11 11 r/w rtcporb 0 memb12 12 r/w rtcporb 0 memb13 13 r/w rtcporb 0 memb14 14 r/w rtcporb 0 memb15 15 r/w rtcporb 0 memb16 16 r/w rtcporb 0 memb17 17 r/w rtcporb 0 memb18 18 r/w rtcporb 0 memb19 19 r/w rtcporb 0 memb20 20 r/w rtcporb 0 memb21 21 r/w rtcporb 0 memb22 22 r/w rtcporb 0 memb23 23 r/w rtcporb 0 table 132. register 20, rtc time name bit # r/w reset default description tod0 0 r/w rtcporb 0 time of day counter tod1 1 r/w rtcporb 0 tod2 2 r/w rtcporb 0 tod3 3 r/w rtcporb 0 tod4 4 r/w rtcporb 0 tod5 5 r/w rtcporb 0 tod6 6 r/w rtcporb 0 tod7 7 r/w rtcporb 0 tod8 8 r/w rtcporb 0 tod9 9 r/w rtcporb 0 tod10 10 r/w rtcporb 0 tod11 11 r/w rtcporb 0 tod12 12 r/w rtcporb 0 tod13 13 r/w rtcporb 0 tod14 14 r/w rtcporb 0 tod15 15 r/w rtcporb 0 tod16 16 r/w rtcporb 0 rtccal0 17 r/w rtcporb 0 rtc calibration count rtccal1 18 r/w rtcporb 0 rtccal2 19 r/w rtcporb 0 rtccal3 20 r/w rtcporb 0 rtccal4 21 r/w rtcporb 0
analog integrated circuit device data 134 freescale semiconductor mc13892 spi bitmap rtccalmode0 22 r/w rtcporb 0 rtc calibration mode rtccalmode1 23 r/w rtcporb 0 table 133. register 21, rtc alarm name bit # r/w reset default description toda0 0 r/w rtcporb 1 time of day alarm toda1 1 r/w rtcporb 1 toda2 2 r/w rtcporb 1 toda3 3 r/w rtcporb 1 toda4 4 r/w rtcporb 1 toda5 5 r/w rtcporb 1 toda6 6 r/w rtcporb 1 toda7 7 r/w rtcporb 1 toda8 8 r/w rtcporb 1 toda9 9 r/w rtcporb 1 toda10 10 r/w rtcporb 1 toda11 11 r/w rtcporb 1 toda12 12 r/w rtcporb 1 toda13 13 r/w rtcporb 1 toda14 14 r/w rtcporb 1 toda15 15 r/w rtcporb 1 toda16 16 r/w rtcporb 1 spare 17 r/w rtcporb 0 for future use spare 18 r/w rtcporb 0 spare 19 r/w rtcporb 0 spare 20 r/w rtcporb 0 spare 21 r/w rtcporb 0 spare 22 r/w rtcporb 0 rtcdis 23 r/w rtcporb 0 disable rtc table 134. register 22, rtc day name bit # r/w reset default description day0 0 r/w rtcporb 0 day counter day1 1 r/w rtcporb 0 day2 2 r/w rtcporb 0 day3 3 r/w rtcporb 0 day4 4 r/w rtcporb 0 day5 5 r/w rtcporb 0 day6 6 r/w rtcporb 0 day7 7 r/w rtcporb 0 day8 8 r/w rtcporb 0 day9 9 r/w rtcporb 0 day10 10 r/w rtcporb 0 day11 11 r/w rtcporb 0 day12 12 r/w rtcporb 0 day13 13 r/w rtcporb 0 day14 14 r/w rtcporb 0 table 132. register 20, rtc time name bit # r/w reset default description
analog integrated circuit device data freescale semiconductor 135 mc13892 spi bitmap unused 15 r 0 not available unused 16 r 0 unused 17 r 0 unused 18 r 0 unused 19 r 0 unused 20 r 0 unused 21 r 0 unused 22 r 0 unused 23 r 0 table 135. register 23, rtc day alarm name bit # r/w reset default description daya0 0 r/w rtcporb 1 day alarm daya1 1 r/w rtcporb 1 daya2 2 r/w rtcporb 1 daya3 3 r/w rtcporb 1 daya4 4 r/w rtcporb 1 daya5 5 r/w rtcporb 1 daya6 6 r/w rtcporb 1 daya7 7 r/w rtcporb 1 daya8 8 r/w rtcporb 1 daya9 9 r/w rtcporb 1 daya10 10 r/w rtcporb 1 daya11 11 r/w rtcporb 1 daya12 12 r/w rtcporb 1 daya13 13 r/w rtcporb 1 daya14 14 r/w rtcporb 1 unused 15 r 0 not available unused 16 r 0 unused 17 r 0 unused 18 r 0 unused 19 r 0 unused 20 r 0 unused 21 r 0 unused 22 r 0 unused 23 r 0 table 136. register 24, switchers 0 name bit # r/w reset default description sw10 0 r/w none * sw1 setting in normal mode sw11 1 r/w none * sw12 2 r/w none * sw13 3 r/w none * sw14 4 r/w none * table 134. register 22, rtc day name bit # r/w reset default description
analog integrated circuit device data 136 freescale semiconductor mc13892 spi bitmap sw1dvs0 5 r/w none * sw1 setting in dvs mode sw1dvs1 6 r/w none * sw1dvs2 7 r/w none * sw1dvs3 8 r/w none * sw1dvs4 9 r/w none * sw1stby0 10 r/w none * sw1 setting in standby mode sw1stby1 11 r/w none * sw1stby2 12 r/w none * sw1stby3 13 r/w none * sw1stby4 14 r/w none * sw1sidmax0 15 r/w resetb 0 sw1 sid mode maximum level sw1sidmax1 16 r/w resetb 1 sw1sidmax2 17 r/w resetb 0 sw1sidmax3 18 r/w resetb 1 sw1sidmin0 19 r/w resetb 0 sw1 sid mode minimum level (leading 0 implied) sw1sidmin1 20 r/w resetb 0 sw1sidmin2 21 r/w resetb 0 sw1sidmin3 22 r/w resetb 1 sw1hi 23 r/w none * sw1 output range selection table 137. register 25, switchers 1 name bit # r/w reset default description sw20 0 r/w none * sw2 setting in normal mode sw21 1 r/w none * sw22 2 r/w none * sw23 3 r/w none * sw24 4 r/w none * sw2dvs0 5 r/w none * sw2 setting in dvs mode sw2dvs1 6 r/w none * sw2dvs2 7 r/w none * sw2dvs3 8 r/w none * sw2dvs4 9 r/w none * sw2stby0 10 r/w none * sw2 setting in standby mode sw2stby1 11 r/w none * sw2stby2 12 r/w none * sw2stby3 13 r/w none * sw2stby4 14 r/w none * sw2sidmax0 15 r/w resetb 0 sw2 sid mode maximum level sw2sidmax1 16 r/w resetb 1 sw2sidmax2 17 r/w resetb 0 sw2sidmax3 18 r/w resetb 1 sw2sidmin0 19 r/w resetb 0 sw2 sid mode minimum level (leading 0 implied) sw2sidmin1 20 r/w resetb 0 sw2sidmin2 21 r/w resetb 0 sw2sidmin3 22 r/w resetb 1 sw2hi 23 r/w none * sw2 output range selection table 136. register 24, switchers 0 name bit # r/w reset default description
analog integrated circuit device data freescale semiconductor 137 mc13892 spi bitmap table 138. register 26, switchers 2 name bit # r/w reset default description sw30 0 r/w none * sw3 setting in normal mode sw31 1 r/w none * sw32 2 r/w none * sw33 3 r/w none * sw34 4 r/w none * spare 5 r/w none * for future use spare 6 r/w none * spare 7 r/w none * spare 8 r/w none * spare 9 r/w none * sw3stby0 10 r/w none * sw3 setting in standby mode sw3stby1 11 r/w none * sw3stby2 12 r/w none * sw3stby3 13 r/w none * sw3stby4 14 r/w none * unused 15 r 0 not available unused 16 r 0 unused 17 r 0 unused 18 r 0 unused 19 r 0 unused 20 r 0 unused 21 r 0 reserved 22 r 0 for future use sw3hi 23 r/w none * sw3 output range selection table 139. register 27, switchers 3 name bit # r/w reset default description sw40 0 r/w none * sw4 setting in normal mode sw41 1 r/w none * sw42 2 r/w none * sw43 3 r/w none * sw44 4 r/w none * spare 5 r/w none * for future use spare 6 r/w none * spare 7 r/w none * spare 8 r/w none * spare 9 r/w none * sw4stby0 10 r/w none * sw4 setting in standby mode sw4stby1 11 r/w none * sw4stby2 12 r/w none * sw4stby3 13 r/w none * sw4stby4 14 r/w none *
analog integrated circuit device data 138 freescale semiconductor mc13892 spi bitmap unused 15 r 0 not available unused 16 r 0 unused 17 r 0 unused 18 r 0 unused 19 r 0 unused 20 r 0 unused 21 r 0 unused 22 r 0 sw4hi 23 r/w none * sw4 output range selection table 140. register 28, switchers 4 name bit # r/w reset default description sw1mode0 0 r/w resetb 0 sw1 operating mode sw1mode1 1 r/w resetb 1 sw1mode2 2 r/w resetb 0 sw1mode3 3 r/w resetb 1 sw1mhmode 4 r/w offb 0 sw1 memory hold mode sw1uomode 5 r/w offb 0 sw1 user off mode sw1dvsspeed0 6 r/w resetb 1 sw1 dvs speed setting sw1dvsspeed1 7 r/w resetb 0 siden 8 r/w resetb 0 sid mode enable reserved 9 r 0 for future use sw2mode0 10 r/w resetb 0 sw2 operating mode sw2mode1 11 r/w resetb 1 sw2mode2 12 r/w resetb 0 sw2mode3 13 r/w resetb 1 sw2mhmode 14 r/w offb 0 sw2 memory hold mode sw2uomode 15 r/w offb 0 sw2 user off mode sw2dvsspeed0 16 r/w resetb 1 sw2 dvs speed setting sw2dvsspeed1 17 r/w resetb 0 pllen 18 r/w resetb 0 switcher pll enable pllx0 19 r/w resetb 0 switcher pll multiplication factor pllx1 20 r/w resetb 0 pllx2 21 r/w resetb 1 swilimb 22 r/w resetb 0 switcher current limit disable reserved 23 r 0 for future use notes 97. swxmode[3:0] bits will be reset to t heir default values by the startup sequencer based on pums settings. an enabled switch er will default to pwm mode (no pulse skipping) for both normal and standby operation. table 141. register 29, switchers 5 name bit # r/w reset default description sw3mode0 0 r/w resetb 0 sw3 operating mode sw3mode1 1 r/w resetb 1 sw3mode2 2 r/w resetb 0 sw3mode3 3 r/w resetb 1 sw3mhmode 4 r/w offb 0 sw3 memory hold mode sw3uomode 5 r/w offb 0 sw3 user off mode table 139. register 27, switchers 3 name bit # r/w reset default description
analog integrated circuit device data freescale semiconductor 139 mc13892 spi bitmap unused 6 r 0 not available unused 7 r 0 sw4mode0 8 r/w resetb 0 sw4 operating mode sw4mode1 9 r/w resetb 1 sw4mode2 10 r/w resetb 0 sw4mode3 11 r/w resetb 1 sw4mhmode 12 r/w offb 0 sw4 memory hold mode sw4uomode 13 r/w offb 0 sw4 user off mode unused 14 r 0 not available unused 15 r 0 unused 16 r 0 unused 17 r 0 unused 18 r 0 unused 19 r 0 swbsten 20 r/w none * swbst enable unused 21 r 0 not available unused 22 r 0 unused 23 r 0 notes 98. swxmode[3:0] bits will be reset to their default values by the startup sequencer based on pu ms settings. an enabled switch er will default to pwm mode (no pulse skippi ng) for both normal and standby operation. table 142. register 30, regulator setting 0 name bit # r/w reset default description vgen10 0 r/w resetb 0 vgen1 setting vgen11 1 r/w resetb 0 unused 2 r 0 not available unused 3 r 0 vdig0 4 r/w none * vdig setting vdig1 5 r/w none * vgen20 6 r/w none * vgen2 setting vgen21 7 r/w none * vgen22 8 r/w none * vpll0 9 r/w none * vpll setting vpll1 10 r/w none * vusb20 11 r/w none * vusb2 setting vusb21 12 r/w none * unused 13 r 0 not available vgen3 14 r/w resetb 1 vgen3 setting unused 15 r 0 not available vcam0 16 r/w resetb 0 vcam setting vcam1 17 r/w resetb 1 spare 18 r/w resetb 0 for future use unused 19 r 0 not available unused 20 r 0 not available unused 21 r 0 not available unused 22 r 0 not available unused 23 r 0 not available table 141. register 29, switchers 5 name bit # r/w reset default description
analog integrated circuit device data 140 freescale semiconductor mc13892 spi bitmap table 143. register 31, regulator setting 1 name bit # r/w reset default description reserved 0 r 0 for future use reserved 1 r 0 vvideo0 2 r/w resetb 0 vvideo setting vvideo1 3 r/w resetb 1 vaudio0 4 r/w resetb 1 vaudio setting vaudio1 5 r/w resetb 0 vsd10 6 r/w resetb 1 vsd setting vsd11 7 r/w resetb 1 vsd12 8 r/w resetb 1 unused 9 r 0 not available unused 10 r 0 unused 11 r 0 unused 12 r 0 unused 13 r 0 unused 14 r 0 unused 15 r 0 unused 16 r 0 unused 17 r 0 unused 18 r 0 unused 19 r 0 unused 20 r 0 unused 21 r 0 unused 22 r 0 unused 23 r 0 table 144. register 32, regulator mode 0 name bit # r/w reset default description vgen1en 0 r/w resetb 0 vgen1 enable vgen1stby 1 r/w resetb 0 vgen1 controlled by standby vgen1mode 2 r/w resetb 0 vgen1 operating mode viohien 3 r/w none * viohi enable viohistby 4 r/w resetb 0 viohi controlled by standby spare 5 r/w resetb 0 for future use unused 6 r 0 not available unused 7 r 0 not available unused 8 r 0 not available vdigen 9 r/w none * vdig enable vdigstby 10 r/w resetb 0 vdig controlled by standby spare 11 r/w resetb 0 for future use vgen2en 12 r/w none * vgen2 enable vgen2stby 13 r/w resetb 0 vgen2 controlled by standby vgen2mode 14 r/w resetb 0 vgen2 operating mode vpllen 15 r/w none * vpll enable vpllstby 16 r/w resetb 0 vpll controlled by standby spare 17 r/w resetb 0 for future use vusb2en 18 r/w resetb 0 vusb2 enable vusb2stby 19 r/w resetb 0 vusb2 controlled by standby spare 20 r/w resetb 0 for future use
analog integrated circuit device data freescale semiconductor 141 mc13892 spi bitmap unused 21 r 0 not available unused 22 r 0 unused 23 r 0 table 145. register 33, regulator mode 1 name bit # r/w reset default description vgen3en 0 r/w resetb 0 vgen3 enable vgen3stby 1 r/w resetb 0 vgen3controlled by standby vgen3mode 2 r/w resetb 0 vgen3 operating mode vgen3config 3 r/w resetb 0 vgen3 with external pnp reserved 4 r 0 for future use spare 5 r/w resetb 0 for future use vcamen 6 r/w resetb 0 vcam enable vcamstby 7 r/w resetb 0 vcam controlled by standby vcammode 8 r/w resetb 0 vcam operating mode vcamconfig 9 r/w resetb 0 vcam with external pnp unused 10 r 0 not available reserved 11 r 0 for future use vvideoen 12 r/w resetb 0 vvideo enable videostby 13 r/w resetb 0 vvideo controlled by standby vvideomode 14 r/w resetb 0 vvideo operating mode vaudioen 15 r/w resetb 0 vaudio enable vaudiostby 16 r/w resetb 0 vaudio controlled by standby spare 17 r/w resetb 0 for future use vsden 18 r/w resetb 0 vsd enable vsdstby 19 r/w resetb 0 vsd controlled by standby vsdmode 20 r/w resetb 0 vsd operating mode unused 21 r 0 not available unused 22 r 0 unused 23 r 0 table 146. register 34, power miscellaneous name bit # r/w reset default description regscpen 0 r/w resetb 0 regulator short circuit protection enable unused 1 r 0 not available unused 2 r 0 unused 3 r 0 unused 4 r 0 unused 5 r 0 gpo1en 6 r/w resetb 0 gpo1 enable gpo1stby 7 r/w resetb 0 gpo1 controlled by standby gpo2en 8 r/w resetb 0 gpo2 enable gpo2stby 9 r/w resetb 0 gpo2 controlled by standby gpo3en 10 r/w resetb 0 gpo3 enable gpo3stby 11 r/w resetb 0 gpo3 controlled by standby gpo4en 12 r/w resetb 0 gpo4 enable gpo4stby 13 r/w resetb 0 gpo4 controlled by standby unused 14 r 0 not available table 144. register 32, regulator mode 0 name bit # r/w reset default description
analog integrated circuit device data 142 freescale semiconductor mc13892 spi bitmap pwgt1spien 15 r/w resetb 1 power gate 1 enable pwgt2spien 16 r/w resetb 1 power gate 2 enable spare 17 r/w resetb 0 for future use unused 18 r 0 not available unused 19 r 0 unused 20 r 0 gpo4adin 21 r/w resetb 1 gpo4 configured as adc input (gpo drive tri-stated) unused 22 r 0 not available unused 23 r 0 table 147. register 35, unused name bit # r/w reset default description unused 23-0 r 0 not available table 148. register 36, unused name bit # r/w reset default description unused 23-0 r 0 not available table 149. register 37, unused name bit # r/w reset default description unused 23-0 r 0 not available table 150. register 38, unused name bit # r/w reset default description unused 23-0 r 0 not available table 151. register 39, unused name bit # r/w reset default description unused 23-0 r 0 not available table 152. register 40, unused name bit # r/w reset default description unused 23-0 r 0 not available table 153. register 41, unused name bit # r/w reset default description unused 23-0 r 0 not available table 154. register 42, unused name bit # r/w reset default description unused 23-0 r 0 not available table 146. register 34, power miscellaneous name bit # r/w reset default description
analog integrated circuit device data freescale semiconductor 143 mc13892 spi bitmap table 155. register 43, adc 0 name bit # r/w reset default description licellcon 0 r/w resetb 0 enables lithium cell reading chrgicon 1 r/w resetb 0 enables charge current reading baticon 2 r/w resetb 0 enables battery current reading buffen 3 r/w resetb 0 input buffer enable adin7sel0 4 r/w resetb 0 gp adc channel 7 mux selection 0 adin7sel1 5 r/w resetb 0 gp adc channel 7 mux selection 1 unused 6 r 0 not available unused 7 r 0 adreset 8 rwm resetb 0 reset gp adc system adin7div 9 r/w resetb 0 divide by 2 enable for adin7 tsrefen 10 r/w resetb 0 enables the touch screen reference reserved 11 r 0 for future use tsmod0 12 r/w resetb 0 sets the touch screen interface mode tsmod1 13 r/w resetb 0 tsmod2 14 r/w resetb 0 chrgrawdiv 15 r/w resetb 1 sets chrgraw scaling to divide by 5 adinc1 16 r/w resetb 0 auto increment for ada1 adinc2 17 r/w resetb 0 auto increment for ada2 unused 18 r 0 not available spare 19 r/w resetb 0 for future use unused 20 r 0 not available unused 21 r 0 unused 22 r 0 adcbis0 23 w 0 access to the adcbis control table 156. register 44, adc 1 name bit # r/w reset default description aden 0 r/w resetb 0 enables the adc rand 1 r/w resetb 0 sets the single channel mode adccal 2 rwm resetb 0 adc calibration adsel 3 r/w resetb 0 selects the set of inputs trigmask 4 r/w resetb 0 trigger event masking ada10 5 r/w resetb 0 channel selection 1 ada11 6 r/w resetb 0 ada12 7 r/w resetb 0 ada20 8 r/w resetb 0 channel selection 2 ada21 9 r/w resetb 0 ada22 10 r/w resetb 0 ato0 11 r/w resetb 0 delay before first conversion ato1 12 r/w resetb 0 ato2 13 r/w resetb 0 ato3 14 r/w resetb 0 ato4 15 r/w resetb 0 ato5 16 r/w resetb 0 ato6 17 r/w resetb 0 ato7 18 r/w resetb 0 atox 19 r/w resetb 0 sets ato delay for any conversion asc 20 rwm resetb 0 starts conversion adtrigign 21 r/w resetb 0 ignores the adtrig input
analog integrated circuit device data 144 freescale semiconductor mc13892 spi bitmap adoneshot 22 r/w resetb 0 single trigger event only adcbis1 23 w resetb 0 access to the adcbis control table 157. register 45, adc 2 name bit # r/w reset default description spare 0 r none 0 for 12-bit use spare 1 r none 0 add10 2 r none 0 results for channel selection 1 add11 3 r none 0 add12 4 r none 0 add13 5 r none 0 add14 6 r none 0 add15 7 r none 0 add16 8 r none 0 add17 9 r none 0 add18 10 r none 0 add19 11 r none 0 spare 12 r none 0 for 12-bit use spare 13 r none 0 add20 14 r none 0 results for channel selection 2 add21 15 r none 0 add22 16 r none 0 add23 17 r none 0 add24 18 r none 0 add25 19 r none 0 add26 20 r none 0 add27 21 r none 0 add28 22 r none 0 add29 23 r none 0 table 158. register 46, adc 3 name bit # r/w reset default description unused 0 r 0 not available unused 1 r 0 unused 2 r 0 unused 3 r 0 unused 4 r 0 unused 5 r 0 icid0 6 r none 1 generation id icid1 7 r none 1 icid2 8 r none 1 table 156. register 44, adc 1 name bit # r/w reset default description
analog integrated circuit device data freescale semiconductor 145 mc13892 spi bitmap unused 9 r 0 not available unused 10 r 0 unused 11 r 0 unused 12 r 0 unused 13 r 0 unused 14 r 0 unused 15 r 0 unused 16 r 0 unused 17 r 0 unused 18 r 0 unused 19 r 0 unused 20 r 0 unused 21 r 0 unused 22 r 0 reserved 23 r 0 for future use table 159. register 47, adc 4 name bit # r/w reset default description spare 0 r none 0 for 12-bit use spare 1 r none 0 addbis10 2 r none 0 result for channel selection 1 of adcbis addbis11 3 r none 0 addbis12 4 r none 0 addbis13 5 r none 0 addbis14 6 r none 0 addbis15 7 r none 0 addbis16 8 r none 0 addbis17 9 r none 0 addbis18 10 r none 0 addbis19 11 r none 0 spare 12 r none 0 for 12-bit use spare 13 r none 0 addbis20 14 r none 0 result for channel selection 2 of adcbis addbis21 15 r none 0 addbis22 16 r none 0 addbis23 17 r none 0 addbis24 18 r none 0 addbis25 19 r none 0 addbis26 20 r none 0 addbis27 21 r none 0 addbis28 22 r none 0 addbis29 23 r none 0 table 158. register 46, adc 3 name bit # r/w reset default description
analog integrated circuit device data 146 freescale semiconductor mc13892 spi bitmap table 160. register 48, charger 0 name bit # r/w reset default description vchrg0 0 r/w resetb 1 sets the charge regulator output voltage vchrg1 1 r/w resetb 1 vchrg2 2 r/w resetb 0 ichrg0 3 rwm resetb 0 sets the main charger dac current ichrg1 4 rwm resetb 0 ichrg2 5 rwm resetb 0 ichrg3 6 rwm resetb 0 tren 7 r/w resetb 0 enables the internal trickle charger current acklpb 8 r/w resetb 0 acknowledge low-power boot thchkb 9 r/w resetb 0 battery thermistor check disable fetovrd 10 r/w resetb 0 allows battfet control fetctrl 11 r/w resetb 0 battfet control spare 12 r/w resetb 0 for future use rvrsmode 13 rwm resetb 0 reverse mode enable unused 14 r 0 not available plim0 15 r/w resetb 0 power limiter setting plim1 16 r/w resetb 0 plimdis 17 r/w resetb 0 power limiter disable chrgleden 18 r/w resetb 0 chrgled enable chgtmrrst 19 rwm resetb 0 charge timer reset chgrestart 20 rwm resetb 0 restarts charger state machine chgautob 21 r/w resetb 0 avoids automatic charging while on cyclb 22 r/w resetb 1 disables cycling chgautovib 23 r/w resetb 0 allows v and i programming table 161. register 49, usb 0 name bit # r/w reset default description reserved 0 r 0 for future use reserved 1 r 0 reserved 2 r 0 reserved 3 r 0 reserved 4 r 0 reserved 5 r 0 spare 6 r/w resetb 1 reserved 7 r 0 reserved 8 r 0 for future use reserved 9 r 0 reserved 10 r 0 reserved 11 r 0 reserved 12 r 0 reserved 13 r 0 reserved 14 r 0 reserved 15 r 0 reserved 16 r 0 unused 17 r 0 not available unused 18 r 0 reserved 19 r 0 for future use reserved 20 r 0 reserved 21 r 0
analog integrated circuit device data freescale semiconductor 147 mc13892 spi bitmap idpucntrl 22 r/w resetb 0 uid pin pull up source select reserved 23 r 0 for future use table 162. register 50, charger usb 1 name bit # r/w reset default description vusbin 0 r/w none * slave or host configuration for vbus unused 1 r 0 not available unused 2 r 0 vusben 3 r/w resetb 1 vusb enable (pums2=open) also reset to 1 by invalid vbus none * vusb enable (pums2=gnd) unused 4 r 0 not available unused 5 r 0 reserved 6 r 0 for future use reserved 7 r 0 id100kpu 8 r/w resetb 0 switches in 100k uid pull-up reserved 9 r 0 for future use otgswbsten 10 r/w resetb 0 enable swbst for usb otg mode reserved 11 r 0 for future use reserved 12 r 0 reserved 13 r 0 unused 14 r 0 not available unused 15 r 0 reserved 16 r 0 for future use spare 17 r/w resetb 0 spare 18 r/w resetb 0 for future use unused 19 r 0 not available unused 20 r 0 unused 21 r 0 unused 22 r 0 unused 23 r 0 table 163. register 51, led control 0 name bit # r/w reset default description spare 0 r/w resetb 0 for future use ledmdhi 1 r/w resetb 0 main display driver high current mode ledmdramp 2 r/w resetb 0 main display driver ramp enable ledmddc0 3 r/w resetb 0 main display driver duty cycle ledmddc1 4 r/w resetb 0 ledmddc2 5 r/w resetb 0 ledmddc3 6 r/w resetb 0 ledmddc4 7 r/w resetb 0 ledmddc5 8 r/w resetb 0 ledmd0 9 r/w resetb 0 main display driver current setting ledmd1 10 r/w resetb 0 ledmd2 11 r/w resetb 0 spare 12 r/w resetb 0 for future use ledadhi 13 r/w resetb 0 auxiliary display driver high current mode ledadramp 14 r/w resetb 0 auxiliary display driver ramp enable table 161. register 49, usb 0 name bit # r/w reset default description
analog integrated circuit device data 148 freescale semiconductor mc13892 spi bitmap ledaddc0 15 r/w resetb 0 auxiliary display driver duty cycle ledaddc1 16 r/w resetb 0 ledaddc2 17 r/w resetb 0 ledaddc3 18 r/w resetb 0 ledaddc4 19 r/w resetb 0 ledaddc5 20 r/w resetb 0 ledad0 21 r/w resetb 0 auxiliary display driver current setting ledad1 22 r/w resetb 0 ledad2 23 r/w resetb 0 table 164. register 52, led control 1 name bit # r/w reset default description spare 0 r/w resetb 0 for future use ledkphi 1 r/w resetb 0 keypad driver high current mode ledkpramp 2 r/w resetb 0 keypad driver ramp enable ledkpdc0 3 r/w resetb 0 keypad driver duty cycle ledkpdc1 4 r/w resetb 0 ledkpdc2 5 r/w resetb 0 ledkpdc3 6 r/w resetb 0 ledkpdc4 7 r/w resetb 0 ledkpdc5 8 r/w resetb 0 ledkp0 9 r/w resetb 0 keypad driver current setting ledkp1 10 r/w resetb 0 ledkp2 11 r/w resetb 0 spare 12 r/w resetb 0 for future use spare 13 r/w resetb 0 spare 14 r/w resetb 0 unused 15 r 0 not available unused 16 r 0 not available unused 17 r 0 unused 18 r 0 unused 19 r 0 unused 20 r 0 unused 21 r 0 unused 22 r 0 unused 23 r 0 table 165. register 53, led control 2 name bit # r/w reset default description ledrper0 0 r/w resetb 0 red channel blink period ledrper1 1 r/w resetb 0 ledrramp 2 r/w resetb 0 red channel driver ramp enable ledrdc0 3 r/w resetb 0 red channel driver duty cycle ledrdc1 4 r/w resetb 0 ledrdc2 5 r/w resetb 0 ledrdc3 6 r/w resetb 0 ledrdc4 7 r/w resetb 0 ledrdc5 8 r/w resetb 0 table 163. register 51, led control 0 name bit # r/w reset default description
analog integrated circuit device data freescale semiconductor 149 mc13892 spi bitmap ledr0 9 r/w resetb 0 red channel driver current setting ledr1 10 r/w resetb 0 ledr2 11 r/w resetb 0 ledgper0 12 r/w resetb 0 green channel blink period ledgper1 13 r/w resetb 0 ledgramp 14 r/w resetb 0 green channel driver ramp enable ledgdc0 15 r/w resetb 0 green channel driver duty cycle ledgdc1 16 r/w resetb 0 ledgdc2 17 r/w resetb 0 ledgdc3 18 r/w resetb 0 ledgdc4 19 r/w resetb 0 ledgdc5 20 r/w resetb 0 ledg0 21 r/w resetb 0 green channel driver current setting ledg1 22 r/w resetb 0 ledg2 23 r/w resetb 0 table 166. register 54, led control 3 name bit # r/w reset default description ledbper0 0 r/w resetb 0 blue channel blink period ledbper1 1 r/w resetb 0 ledbramp 2 r/w resetb 0 blue channel driver ramp enable ledbdc0 3 r/w resetb 0 blue channel driver duty cycle ledbdc1 4 r/w resetb 0 ledbdc2 5 r/w resetb 0 ledbdc3 6 r/w resetb 0 ledbdc4 7 r/w resetb 0 ledbdc5 8 r/w resetb 0 ledb0 9 r/w resetb 0 blue channel driver current setting ledb1 10 r/w resetb 0 ledb2 11 r/w resetb 0 ledswbsten 12 r/w resetb 0 enable swbst for rgb led?s spare 13 r/w resetb 0 for future use spare 14 r/w resetb 0 unused 15 r 0 not available unused 16 r 0 unused 17 r 0 unused 18 r 0 unused 19 r 0 unused 20 r 0 unused 21 r 0 unused 22 r 0 unused 23 r 0 table 167. register 55, not used name bit # r/w reset default description unused 23-0 r 0 not available table 165. register 53, led control 2 name bit # r/w reset default description
analog integrated circuit device data 150 freescale semiconductor mc13892 spi bitmap table 168. register 56, not used name bit # r/w reset default description unused 23-0 r 0 not available table 169. register 57, fsl use only name bit # r/w reset default description fsl use only 23-0 r/w rtcporb fsl table 170. register 58, fsl use only name bit # r/w reset default description fsl use only 23-0 r/w rtcporb fsl table 171. register 59, fsl use only name bit # r/w reset default description fsl use only 23-0 r/w rtcporb fsl table 172. register 60, fsl use only name bit # r/w reset default description fsl use only 23-0 r/w rtcporb fsl table 173. register 61, fsl use only name bit # r/w reset default description fsl use only 23:0 r/w rtcporb fsl table 174. register 62, fsl use only name bit # r/w reset default description fsl use only 23:0 r/w rtcporb fsl table 175. register 63, fsl use only name bit # r/w reset default description fsl use only 23:0 r/w rtcporb fsl
analog integrated circuit device data freescale semiconductor 151 mc13892 typical applications typical applications figure 35 contains a typical application of the mc13892. for c onvenience, components for use with the mc13892 are cited within this document. freescale does not assume liability, endorse , or warrant components from external manufacturers that are referenced in circuit drawings or tables. while freescale offe rs component recommendations in th is configuration, it is the customer?s responsibility to validate their application. figure 35. mc13892 typical application tsy1 tsy2 bpsns bp resetb resetbmcu wdi standbysec switchers adtrig gndadc adin7 mux 10 bit gp adc int clk32k xtal1 xtal2 gndrtc licell gpo control gpo1 gpo2 rtc + calibration gndsw2 sw2fb sw2out sw1in sw1 1050 ma buck sw2in o/p drive gndsw1 sw1fb sw1out sw3in o/p drive gndsw3 sw3fb sw3out gndswbst swbstfb swbstin swbstout o/p drive pwron1 pums1 monitor timer o/p drive pll 32 khz crystal osc standby gpo3 pwgtdrv1 pwr gate drive & chg pump to interrupt section die temp & thermal warning detection lcell switch enables & control spi result registers interrupt inputs gndctrl core control logic, timers, & interrupts 32 khz internal osc gpo4 chrgctrl1 chrgisns chrgraw chrgled batt battisns battfet bp battery interface & protection licell, uid, die temp, gpo4 adin6 gndchrg clk32kmcu gndreg1 gndreg2 dvs2 dvs1 adin5 a/d result a/d control trigger handling chrgse1b mode dvs control 32 khz buffers chrgctrl2 output pin input pin bi-directional pin package pin legend mc13892 ic charger interface and control: 4 bit dac, clamp, protection, trickle generation pwgtdrv2 spi interface + muxed i2c optional interface cs clk gndspi miso spi registers mosi shift register shift register spivcc to enables & control to trimmed circuits spi control logic trim-in-package startup sequencer decode trim? pums control logic li cell charger sw2 800 ma buck sw3 800 ma buck swbst 300 ma boost voltage / current sensing & translation ledmd ledad ledkp backlight led drive gndbl mc13892 tsx2 tsx1 tsref touch screen interface coulomb counter cfp cfm battisnscc batt ccout to spi sw4in o/p drive gndsw4 sw4fb sw4out sw4 800 ma buck vsrtc vsrtc gndled ledr ledg ledb tri-color led drive vindig vpll vviohi pass fet vpll pass fet vdig pass fet vgen1 vdig viniohi viohi vgen1drv vgen1 vcam pass fet vincamdrv vcam vsddrv vsd pass fet vusb2 vvideodrv vvideo vvideo vinusb2 vusb2 spi control vgen2 vgen2drv vgen2 vsd uvbus vinusb vusb uid connector interface best of supply licell bp vgen3 vingen3drv vgen3 gndsub4 gndsub3 gndsub2 gndsub1 gndsub8 gndsub7 gndsub6 gndsub5 reference generation vcoredig gndcore vcore refcore vbus/id detectors vusb regulator otg 5v vbusen vaudio pass fet vaudio 32.768 khz crystal 18p 18p to gnd, open, vcoredig or vcore to/from ap on/off button to/from peripherals to/from ap possible applications, may also be used for enables to adjunct supplies or modules as necessary to thermistor bias to light sensor enable to external audio enable to external camera flash or aux light sensor 2.2u 2.2u bp 2.2u 2.2u 2.2u bp 2.2u bp bp 2.2u bp bp bp 2.2u 2.2u bp 2.2u bp 2.2u bp 10u swbst output (boost) 2.2u from ap from ap 1.5u 2 x22u bp sw1 output 2.2u 10u sw2 output 10u sw3 output 2.2u 10u 2.2u sw4 output sw4 to memory to 1.8v peripherals sw3 processor internal memory to 1.2v peripherals user off user off, memory hold swbst bp from extenal boost ap cspi general purpose adc inputs: i.e., battery pack thermistor, pa thermistor, light sensor, etc. sw4 from ap touch screen interface charger/usb input (tied to vbus) bp r1 20m r2 100m m3 m2 m1 2.2u 10u 10u 100n 2.2u 10uf chrgraw id from ap swbst 2.2u 100n coin cell battery main battery gndsub9 gndreg3 bp viinaudio bp vinpll pums2 hold switch pwron2 from docking station pwron3 tied to battisnscc from m3/r1 connection (needs to be separate route from battisns) pass fet 2.2u to/from usb cable 1.0u bp 4.7u bp 4.7u bp 4.7u bp 4.7u 4.7u
analog integrated circuit device data 152 freescale semiconductor mc13892 packaging package dimensions packaging package dimensions for the most current pa ckage revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. vk suffix 139-pin 98asa10820d revision 0
analog integrated circuit device data freescale semiconductor 153 mc13892 packaging package dimensions vk suffix 139-pin 98asa10820d revision 0
analog integrated circuit device data 154 freescale semiconductor mc13892 packaging package dimensions vl suffix 186-pin 98asa10849d revision 0
analog integrated circuit device data freescale semiconductor 155 mc13892 packaging package dimensions vl suffix 186-pin 98asa10849d revision 0
analog integrated circuit device data 156 freescale semiconductor mc13892 additional documentation additional documentation table 176. additional documentation document number description mc13892er mc13892er, silicon mask errata mc13783 mc13783, power management and audio circuit
analog integrated circuit device data freescale semiconductor 157 mc13892 revision history revision history revision date description 14.0 11/2011 ? added mc13892cjvk and mc13892cjvl to the ordering information ? changed rt from 45 k to 4.5 k in table 73 for t high ? in the static electrical characteristics tabl e, changed input operating voltage - chrgraw from 17 v to 5.6 v on page 24. ? changed input operating voltage - chrgraw from 17 v to 5.6 v in table 64 . 15.0 4/2012 ? added mc13892djvk and MC13892DJVL to table 1, mc13892 device variations . 16.0 4/2012 ? corrected global reset functions in table 1 17.0 5/2012 ? clarified the global reset function for silic on versions a, b, c and d throughout the document ? section pwron1, 2 and 3 on page 37 ? section global system restart on page 60 ? table 125, register 13, power control 0
document number: mc13892 rev. 17.0 05/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fa bricate any integrated circuits on the information in this document. freescale reserves the right to make chang es without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particul ar purpose, nor does freescale assume any liability arising out of the application or us e of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differ ent applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s te chnical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/freescale/docs/termsandconditions.htm freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, mobilegt, powerquicc, qoriq, qorivva, starcore, and symphony are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, co renet, flexis, magniv, mxc, platform in a package, processor expert, qoriq qonverge, quicc engine, ready play, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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